soc/intel/jasperlake: Add VR Configuration settings

This CL fixes the CPU Throttling issue.

BUG=b:167472333
TEST=Build and boot dedede and observe the slope and offset values
     getting updated in the fsp debug log

Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Change-Id: I3fa32218040263f0abef8b9dd4c52efb31289fd7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45645
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>

src/soc/intel/jasperlake/chip.h

@@ -136,6 +136,10 @@ struct soc_intel_jasperlake_config {
 	/* Heci related */
 	uint8_t Heci3Enabled;
 
+	/* VR Config Settings for IA Core */
+	uint16_t ImonSlope;
+	uint16_t ImonOffset;
+
 	/* Gfx related */
 	uint8_t IgdDvmt50PreAlloc;
 	uint8_t InternalGfx;

src/soc/intel/jasperlake/fsp_params.c

@@ -177,6 +177,10 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 				sizeof(params->SataPortsDevSlp));
 	}
 
+	/* VR Configuration */
+	params->ImonSlope[0] = config->ImonSlope;
+	params->ImonOffset[0] = config->ImonOffset;
+
 	/* SDCard related configuration */
 	dev = pcidev_path_on_root(PCH_DEVFN_SDCARD);
 	params->ScsSdCardEnabled = is_dev_enabled(dev);