From 5b51faaaea48adf49429d4bfb96d88d9e5d9e08c Mon Sep 17 00:00:00 2001 From: Felix Held Date: Fri, 18 Mar 2022 16:57:22 +0100 Subject: [PATCH] mb/google/skyrim/devicetree: set PSPP policy to DXIO_PSPP_DISABLED Right now, the PSPP policy that controls if the PCIe lanes can be dynamically downgraded to a lower speed to save some power needs to be disabled in order for the link training to be successful. Once this feature is working, PSPP will be reenabled. Signed-off-by: Felix Held Change-Id: I6ea602596acb8e5ea92076386e80102c3bc757af Reviewed-on: https://review.coreboot.org/c/coreboot/+/62924 Tested-by: build bot (Jenkins) Reviewed-by: Raul Rangel Reviewed-by: Jon Murphy --- src/mainboard/google/skyrim/variants/baseboard/devicetree.cb | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/mainboard/google/skyrim/variants/baseboard/devicetree.cb b/src/mainboard/google/skyrim/variants/baseboard/devicetree.cb index 7d4fb7f549..03bb55eee8 100644 --- a/src/mainboard/google/skyrim/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/skyrim/variants/baseboard/devicetree.cb @@ -47,6 +47,8 @@ chip soc/amd/sabrina register "i2c_pad[2].rx_level" = "I2C_PAD_RX_1_8V" # Audio/SAR register "i2c_pad[3].rx_level" = "I2C_PAD_RX_1_8V" # GSC + register "pspp_policy" = "DXIO_PSPP_DISABLED" # TODO: reenable when PSPP works + device domain 0 on device ref lpc_bridge on chip ec/google/chromeec