soc/intel/jasperlake: CNVi: Enable fewer wakeups to reduce SoC power consumption

According to Intel TA#724456, work around the higher SoC power
consumption in S0iX when CNVI has background activity.

BUG=b:201263040
TEST=Turn on this setting and build and verify on Drawcia.
     The SLP_S0 toggling become slower or gone at the same CNVI
     background activity.

Change-Id: I56439a406547e2ee1e47d34be14ecc9a8df04693
Signed-off-by: Jamie Chen <jamie.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63675
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Jamie Chen 2022-03-15 16:16:30 +08:00 committed by Felix Held
parent b30f8687b2
commit 5b58902749
3 changed files with 23 additions and 0 deletions

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@ -421,6 +421,19 @@ struct soc_intel_jasperlake_config {
CD_CLOCK_652_8_MHZ = 9,
} cd_clock;
/*
* This is a workaround to mitigate higher SoC power consumption in S0ix
* when the CNVI has background activity.
*
* Setting this on a system that supports S0i3 (set xtalsdqdis [Bit 22] in
* cppmvric1 register to 0) will break CNVI timing.
* Affected Intel wireless chipsets: AC9560 (JfP2), AC9461/AC9462 (JfP1) and
* AX201 (HrP2)
*
* true: Enabled (fewer wakes, lower power)
* false: Disabled (more wakes, higher power)
*/
bool cnvi_reduce_s0ix_pwr_usage;
};
typedef struct soc_intel_jasperlake_config config_t;

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@ -59,6 +59,11 @@ static void pch_finalize(void)
reg32 = read32(pmcbase + CPPMVRIC3);
reg32 &= ~USBSUSPGQDIS;
write32(pmcbase + CPPMVRIC3, reg32);
if (config->cnvi_reduce_s0ix_pwr_usage) {
setbits32(pmcbase + CPPMVRIC2, CNVIVNNAONREQQDIS);
setbits32(pmcbase + CORE_SPARE_GCR_0, BIT(0));
}
}
pch_handle_sideband(config);

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@ -121,9 +121,14 @@
#define SLP_S0_RES 0x193c
#define CORE_SPARE_GCR_0 0x195C
#define CPPMVRIC 0x1B1C
#define XTALSDQDIS (1 << 22)
#define CPPMVRIC2 0x1B4C
#define CNVIVNNAONREQQDIS (1 << 26)
#define CPPMVRIC3 0x1E4C
#define USBSUSPGQDIS (1 << 15)