soc/intel/jasperlake: CNVi: Enable fewer wakeups to reduce SoC power consumption
According to Intel TA#724456, work around the higher SoC power consumption in S0iX when CNVI has background activity. BUG=b:201263040 TEST=Turn on this setting and build and verify on Drawcia. The SLP_S0 toggling become slower or gone at the same CNVI background activity. Change-Id: I56439a406547e2ee1e47d34be14ecc9a8df04693 Signed-off-by: Jamie Chen <jamie.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63675 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -421,6 +421,19 @@ struct soc_intel_jasperlake_config {
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CD_CLOCK_652_8_MHZ = 9,
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} cd_clock;
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/*
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* This is a workaround to mitigate higher SoC power consumption in S0ix
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* when the CNVI has background activity.
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*
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* Setting this on a system that supports S0i3 (set xtalsdqdis [Bit 22] in
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* cppmvric1 register to 0) will break CNVI timing.
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* Affected Intel wireless chipsets: AC9560 (JfP2), AC9461/AC9462 (JfP1) and
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* AX201 (HrP2)
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*
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* true: Enabled (fewer wakes, lower power)
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* false: Disabled (more wakes, higher power)
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*/
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bool cnvi_reduce_s0ix_pwr_usage;
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};
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typedef struct soc_intel_jasperlake_config config_t;
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@ -59,6 +59,11 @@ static void pch_finalize(void)
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reg32 = read32(pmcbase + CPPMVRIC3);
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reg32 &= ~USBSUSPGQDIS;
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write32(pmcbase + CPPMVRIC3, reg32);
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if (config->cnvi_reduce_s0ix_pwr_usage) {
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setbits32(pmcbase + CPPMVRIC2, CNVIVNNAONREQQDIS);
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setbits32(pmcbase + CORE_SPARE_GCR_0, BIT(0));
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}
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}
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pch_handle_sideband(config);
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@ -121,9 +121,14 @@
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#define SLP_S0_RES 0x193c
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#define CORE_SPARE_GCR_0 0x195C
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#define CPPMVRIC 0x1B1C
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#define XTALSDQDIS (1 << 22)
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#define CPPMVRIC2 0x1B4C
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#define CNVIVNNAONREQQDIS (1 << 26)
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#define CPPMVRIC3 0x1E4C
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#define USBSUSPGQDIS (1 << 15)
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