mb/google/myst: Add PSP verstage callbacks
Lay the groundwork to prepare for enabling PSP verstage. This change adds PSP verstage callback to enable eSPI, TPM etc. BUG=b:284984667 TEST=Build Myst BIOS image with PSP verstage enabled. Change-Id: Ifc800e8bb27cc4c3fbccc2ab9f51138a7c4b03a6 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75585 Reviewed-by: Tim Van Patten <timvp@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
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@ -9,6 +9,8 @@ ramstage-y += mainboard.c
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ramstage-y += port_descriptors.c
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ramstage-$(CONFIG_CHROMEOS) += chromeos.c
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verstage-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += verstage.c
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subdirs-y += variants/baseboard
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subdirs-y += variants/$(VARIANT_DIR)
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@ -8,5 +8,6 @@ romstage-y += gpio.c
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romstage-y += tpm_tis.c
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verstage-y += tpm_tis.c
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verstage-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += gpio.c
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smm-y += smihandler.c
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@ -0,0 +1,39 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <amdblocks/acpimmio.h>
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#include <arch/io.h>
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#include <baseboard/variants.h>
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#include <gpio.h>
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#include <psp_verstage.h>
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#include <security/vboot/vboot_common.h>
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#include <soc/espi.h>
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#include <soc/southbridge.h>
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void verstage_mainboard_early_init(void)
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{
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const struct soc_amd_gpio *gpios;
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size_t num_gpios;
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variant_early_gpio_table(&gpios, &num_gpios);
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gpio_configure_pads(gpios, num_gpios);
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}
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void verstage_mainboard_espi_init(void)
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{
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const struct soc_amd_gpio *gpios;
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size_t num_gpios;
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variant_espi_gpio_table(&gpios, &num_gpios);
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gpio_configure_pads(gpios, num_gpios);
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espi_switch_to_spi1_pads();
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}
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void verstage_mainboard_tpm_init(void)
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{
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const struct soc_amd_gpio *gpios;
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size_t num_gpios;
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variant_tpm_gpio_table(&gpios, &num_gpios);
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gpio_configure_pads(gpios, num_gpios);
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}
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