soc/samsung/exynos: Make 'ps_hold_setup()' static

Change-Id: I272fea9c2767c341e8a545bf7a9ac18eefa2bda5
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7917
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>

src/soc/samsung/exynos5250/power.c

@@ -24,6 +24,7 @@
 #include <halt.h>
 #include "power.h"
 
+/* Set the PS-Hold drive value */
 static void ps_hold_setup(void)
 {
 	/* Set PS-Hold high */

src/soc/samsung/exynos5250/setup.h

@@ -741,8 +741,6 @@ void dmc_config_prech(struct mem_timings *mem, struct exynos5_dmc *dmc);
  */
 void dmc_config_memory(struct mem_timings *mem, struct exynos5_dmc *dmc);
 
-/* Set the PS-Hold drive value */
-void ps_hold_setup(void);
 /*
  * Reset the DLL. This function is common between DDR3 and LPDDR2.
  * However, the reset value is different. So we are passing a flag

src/soc/samsung/exynos5420/power.c

@@ -26,7 +26,8 @@
 #include "power.h"
 #include "setup.h"
 
-void ps_hold_setup(void)
+/* Set the PS-Hold drive value */
+static void ps_hold_setup(void)
 {
 	/* Set PS-Hold high */
 	setbits_le32(&exynos_power->ps_hold_ctrl,

src/soc/samsung/exynos5420/setup.h

@@ -874,8 +874,6 @@ void dmc_config_prech(struct mem_timings *mem, struct exynos5_dmc *dmc);
  */
 void dmc_config_memory(struct mem_timings *mem, struct exynos5_dmc *dmc);
 
-/* Set the PS-Hold drive value */
-void ps_hold_setup(void);
 /*
  * Reset the DLL. This function is common between DDR3 and LPDDR2.
  * However, the reset value is different. So we are passing a flag