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google/veyron_romy: Add new mainboard 

This simply copies veyron_brain to veyron_romy and makes the
minimal set of changes (s/brain/romy) to make it compile. The
follow-up patch will take into account board differences.

BUG=none
BRANCH=none
TEST="emerge-veyron_romy coreboot" doesn't fail

Change-Id: Ice1bc012bddd6c51b43944747e0df3ffa34207fa
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 0ab849178b69cf2323f126e503bd61080048240a
Original-Change-Id: I0516ce94fd3c6a38170fae221a070f503ccfaf0f
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/271345
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/10407
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
This commit is contained in:
David Hendricks 2015-05-13 14:29:23 -07:00 committed by Patrick Georgi
parent 7a8a4ab1d8
commit 5b6645b78d
24 changed files with 1510 additions and 0 deletions
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80
src/mainboard/google/veyron_romy/Kconfig Normal file
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##
## This file is part of the coreboot project.
##
## Copyright 2014 Rockchip Inc.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc.
##
if BOARD_GOOGLE_VEYRON_ROMY
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select BOARD_ID_AUTO
select BOARD_ROMSIZE_KB_4096
select COMMON_CBFS_SPI_WRAPPER
select HAVE_HARD_RESET
select MAINBOARD_DO_NATIVE_VGA_INIT
select MAINBOARD_HAS_CHROMEOS
select RAM_CODE_SUPPORT
select RETURN_FROM_VERSTAGE
select SOC_ROCKCHIP_RK3288
select SPI_FLASH
select SPI_FLASH_GIGADEVICE
select SPI_FLASH_WINBOND
select VIRTUAL_DEV_SWITCH
select CHROMEOS_VBNV_FLASH
config MAINBOARD_DIR
string
default google/veyron_romy
config MAINBOARD_PART_NUMBER
string
default "Veyron_Romy"
config MAINBOARD_VENDOR
string
default "Google"
config BOOT_MEDIA_SPI_BUS
int
default 2
config DRIVER_TPM_I2C_BUS
hex
default 0x1
config DRIVER_TPM_I2C_ADDR
hex
default 0x20
config CONSOLE_SERIAL_UART_ADDRESS
hex
depends on DRIVERS_UART
default 0xFF690000
# FIXME(dhendrix): This is a gross hack intended to get us past
# display init which currently hangs the machine. It will be removed
# once we've re-factored the display init code to properly handle
# various types of displays.
config SKIP_DISPLAY_INIT_HACK
int
default 1
config PMIC_BUS
int
default 0
endif # BOARD_GOOGLE_VEYRON_ROMY

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src/mainboard/google/veyron_romy/Kconfig.name Normal file
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config BOARD_GOOGLE_VEYRON_ROMY
bool "Veyron_Romy"

41
src/mainboard/google/veyron_romy/Makefile.inc Normal file
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##
## This file is part of the coreboot project.
##
## Copyright 2014 Rockchip Inc.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc.
##
bootblock-y += bootblock.c
bootblock-y += boardid.c
bootblock-y += chromeos.c
bootblock-y += reset.c
verstage-y += boardid.c
verstage-y += chromeos.c
verstage-y += reset.c
romstage-y += boardid.c
romstage-y += romstage.c
romstage-y += sdram_configs.c
romstage-y += reset.c
ramstage-y += boardid.c
ramstage-y += chromeos.c
ramstage-y += mainboard.c
ramstage-y += reset.c
bootblock-y += memlayout.ld
verstage-y += memlayout.ld
romstage-y += memlayout.ld
ramstage-y += memlayout.ld

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src/mainboard/google/veyron_romy/board.h Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright 2015 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc.
*/
#ifndef __MAINBOARD_GOOGLE_VEYRON_ROMY_BOARD_H
#define __MAINBOARD_GOOGLE_VEYRON_ROMY_BOARD_H
#include <boardid.h>
#include <gpio.h>
#define GPIO_RESET GPIO(0, B, 5)
void setup_chromeos_gpios(void);
#endif /* __MAINBOARD_GOOGLE_VEYRON_ROMY_BOARD_H */

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src/mainboard/google/veyron_romy/boardid.c Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc.
*/
#include <boardid.h>
#include <console/console.h>
#include <gpio.h>
#include <stdlib.h>
uint8_t board_id(void)
{
static int id = -1;
static gpio_t pins[] = {[3] = GPIO(2, A, 7), [2] = GPIO(2, A, 2),
[1] = GPIO(2, A, 1), [0] = GPIO(2, A, 0)}; /* GPIO2_A0 is LSB */
if (id < 0) {
id = gpio_base2_value(pins, ARRAY_SIZE(pins));
printk(BIOS_SPEW, "Board ID: %d.\n", id);
}
return id;
}
uint32_t ram_code(void)
{
uint32_t code;
static gpio_t pins[] = {[3] = GPIO(8, A, 3), [2] = GPIO(8, A, 2),
[1] = GPIO(8, A, 1), [0] = GPIO(8, A, 0)}; /* GPIO8_A0 is LSB */
code = gpio_base2_value(pins, ARRAY_SIZE(pins));
printk(BIOS_SPEW, "RAM Config: %u.\n", code);
return code;
}

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src/mainboard/google/veyron_romy/bootblock.c Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright 2014 Rockchip Inc.
* Copyright 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc.
*/
#include <arch/io.h>
#include <assert.h>
#include <bootblock_common.h>
#include <console/console.h>
#include <delay.h>
#include <reset.h>
#include <soc/clock.h>
#include <soc/i2c.h>
#include <soc/grf.h>
#include <soc/pmu.h>
#include <soc/rk808.h>
#include <soc/spi.h>
#include <vendorcode/google/chromeos/chromeos.h>
#include "board.h"
void bootblock_mainboard_early_init()
{
if (IS_ENABLED(CONFIG_DRIVERS_UART)) {
assert(CONFIG_CONSOLE_SERIAL_UART_ADDRESS == UART2_BASE);
write32(&rk3288_grf->iomux_uart2, IOMUX_UART2);
}
}
void bootblock_mainboard_init(void)
{
if (rkclk_was_watchdog_reset())
reboot_from_watchdog();
gpio_output(GPIO(7, A, 0), 1); /* Power LED */
/* Up VDD_CPU (BUCK1) to 1.4V to support max CPU frequency (1.8GHz). */
setbits_le32(&rk3288_pmu->iomux_i2c0scl, IOMUX_I2C0SCL);
setbits_le32(&rk3288_pmu->iomux_i2c0sda, IOMUX_I2C0SDA);
assert(CONFIG_PMIC_BUS == 0); /* must correspond with IOMUX */
i2c_init(CONFIG_PMIC_BUS, 400*KHz);
/* Slowly raise to max CPU voltage to prevent overshoot */
rk808_configure_buck(1, 1200);
udelay(175);/* Must wait for voltage to stabilize,2mV/us */
rk808_configure_buck(1, 1400);
udelay(100);/* Must wait for voltage to stabilize,2mV/us */
rkclk_configure_cpu();
/* i2c1 for tpm */
write32(&rk3288_grf->iomux_i2c1, IOMUX_I2C1);
i2c_init(1, 400*KHz);
/* spi2 for firmware ROM */
write32(&rk3288_grf->iomux_spi2csclk, IOMUX_SPI2_CSCLK);
write32(&rk3288_grf->iomux_spi2txrx, IOMUX_SPI2_TXRX);
rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 24750*KHz);
setup_chromeos_gpios();
}

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src/mainboard/google/veyron_romy/chromeos.c Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright 2014 Rockchip Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc.
*/
#include <boot/coreboot_tables.h>
#include <console/console.h>
#include <gpio.h>
#include <string.h>
#include <vendorcode/google/chromeos/chromeos.h>
#include "board.h"
#define GPIO_WP GPIO(7, A, 6)
#define GPIO_POWER GPIO(0, A, 5)
#define GPIO_RECOVERY GPIO(0, B, 1)
void setup_chromeos_gpios(void)
{
gpio_input(GPIO_WP);
gpio_input(GPIO_POWER);
gpio_input_pullup(GPIO_RECOVERY);
}
void fill_lb_gpios(struct lb_gpios *gpios)
{
int count = 0;
/* Write Protect: active low */
gpios->gpios[count].port = GPIO_WP.raw;
gpios->gpios[count].polarity = ACTIVE_LOW;
gpios->gpios[count].value = gpio_get(GPIO_WP);
strncpy((char *)gpios->gpios[count].name, "write protect",
GPIO_MAX_NAME_LENGTH);
count++;
/* Recovery: active low */
gpios->gpios[count].port = GPIO_RECOVERY.raw;
gpios->gpios[count].polarity = ACTIVE_LOW;
gpios->gpios[count].value = gpio_get(GPIO_RECOVERY);
strncpy((char *)gpios->gpios[count].name, "recovery",
GPIO_MAX_NAME_LENGTH);
count++;
/* Power Button: GPIO active low */
gpios->gpios[count].port = GPIO_POWER.raw;
gpios->gpios[count].polarity = ACTIVE_LOW;
gpios->gpios[count].value = -1;
strncpy((char *)gpios->gpios[count].name, "power",
GPIO_MAX_NAME_LENGTH);
count++;
/* Developer: GPIO active high */
gpios->gpios[count].port = -1;
gpios->gpios[count].polarity = ACTIVE_HIGH;
gpios->gpios[count].value = get_developer_mode_switch();
strncpy((char *)gpios->gpios[count].name, "developer",
GPIO_MAX_NAME_LENGTH);
count++;
/* Reset: GPIO active high (output) */
gpios->gpios[count].port = GPIO_RESET.raw;
gpios->gpios[count].polarity = ACTIVE_HIGH;
gpios->gpios[count].value = -1;
strncpy((char *)gpios->gpios[count].name, "reset",
GPIO_MAX_NAME_LENGTH);
count++;
gpios->size = sizeof(*gpios) + (count * sizeof(struct lb_gpio));
gpios->count = count;
printk(BIOS_ERR, "Added %d GPIOS size %d\n", count, gpios->size);
}
int get_developer_mode_switch(void)
{
return 0;
}
int get_recovery_mode_switch(void)
{
return !gpio_get(GPIO_RECOVERY);
}
int get_write_protect_state(void)
{
return !gpio_get(GPIO_WP);
}

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src/mainboard/google/veyron_romy/devicetree.cb Normal file
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##
## This file is part of the coreboot project.
##
## Copyright 2014 Rockchip Inc.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc.
##
# TODO fill with Versatile Express board data in QEMU.
chip soc/rockchip/rk3288
device cpu_cluster 0 on end
register "vop_id" = "1"
register "framebuffer_bits_per_pixel" = "16"
end

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src/mainboard/google/veyron_romy/mainboard.c Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright 2014 Rockchip Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc.
*/
#include <arch/cache.h>
#include <arch/io.h>
#include <boot/coreboot_tables.h>
#include <console/console.h>
#include <delay.h>
#include <device/device.h>
#include <device/i2c.h>
#include <edid.h>
#include <elog.h>
#include <gpio.h>
#include <soc/display.h>
#include <soc/grf.h>
#include <soc/soc.h>
#include <soc/pmu.h>
#include <soc/clock.h>
#include <soc/rk808.h>
#include <soc/spi.h>
#include <soc/i2c.h>
#include <symbols.h>
#include <vbe.h>
#include <vendorcode/google/chromeos/chromeos.h>
#include "board.h"
static void configure_usb(void)
{
gpio_output(GPIO(0, B, 4), 1); /* USBOTG_PWREN_H */
}
static void configure_emmc(void)
{
write32(&rk3288_grf->iomux_emmcdata, IOMUX_EMMCDATA);
write32(&rk3288_grf->iomux_emmcpwren, IOMUX_EMMCPWREN);
write32(&rk3288_grf->iomux_emmccmd, IOMUX_EMMCCMD);
gpio_output(GPIO(2, B, 1), 1); /* EMMC_RST_L */
}
static void configure_codec(void)
{
write32(&rk3288_grf->iomux_i2c2, IOMUX_I2C2); /* CODEC I2C */
i2c_init(2, 400*KHz); /* CODEC I2C */
write32(&rk3288_grf->iomux_i2s, IOMUX_I2S);
write32(&rk3288_grf->iomux_i2sclk, IOMUX_I2SCLK);
rk808_configure_ldo(6, 1800); /* VCC18_CODEC */
/* AUDIO IO domain 1.8V voltage selection */
write32(&rk3288_grf->io_vsel, RK_SETBITS(1 << 6));
rkclk_configure_i2s(12288000);
}
static void configure_vop(void)
{
write32(&rk3288_grf->iomux_lcdc, IOMUX_LCDC);
/* lcdc(vop) iodomain select 1.8V */
write32(&rk3288_grf->io_vsel, RK_SETBITS(1 << 0));
rk808_configure_switch(2, 1); /* VCC18_LCD (HDMI_AVDD_1V8) */
rk808_configure_ldo(7, 1000); /* VDD10_LCD (HDMI_AVDD_1V0) */
rk808_configure_switch(1, 1); /* VCC33_LCD */
}
static void mainboard_init(device_t dev)
{
gpio_output(GPIO_RESET, 0);
configure_usb();
configure_emmc();
configure_codec();
configure_vop();
elog_init();
elog_add_watchdog_reset();
elog_add_boot_reason();
}
static void mainboard_enable(device_t dev)
{
dev->ops->init = &mainboard_init;
}
struct chip_operations mainboard_ops = {
.enable_dev = mainboard_enable,
};
void lb_board(struct lb_header *header)
{
struct lb_range *dma;
dma = (struct lb_range *)lb_new_record(header);
dma->tag = LB_TAB_DMA;
dma->size = sizeof(*dma);
dma->range_start = (uintptr_t)_dma_coherent;
dma->range_size = _dma_coherent_size;
}

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src/mainboard/google/veyron_romy/memlayout.ld Normal file
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#include <soc/memlayout.ld>

30
src/mainboard/google/veyron_romy/reset.c Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc.
*/
#include <arch/io.h>
#include <gpio.h>
#include <reset.h>
#include "board.h"
void hard_reset(void)
{
gpio_output(GPIO_RESET, 1);
while (1);
}

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src/mainboard/google/veyron_romy/romstage.c Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright 2014 Rockchip Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc.
*/
#include <arch/cache.h>
#include <arch/exception.h>
#include <arch/stages.h>
#include <armv7.h>
#include <assert.h>
#include <cbfs.h>
#include <cbmem.h>
#include <console/console.h>
#include <delay.h>
#include <program_loading.h>
#include <soc/sdram.h>
#include <soc/clock.h>
#include <soc/pwm.h>
#include <soc/grf.h>
#include <soc/rk808.h>
#include <soc/tsadc.h>
#include <stdlib.h>
#include <symbols.h>
#include <timestamp.h>
#include <types.h>
#include <vendorcode/google/chromeos/chromeos.h>
#include "board.h"
static void regulate_vdd_log(unsigned int mv)
{
unsigned int duty_ns;
const u32 period_ns = 2000; /* pwm period: 2000ns */
const u32 max_regulator_mv = 1350; /* 1.35V */
const u32 min_regulator_mv = 870; /* 0.87V */
write32(&rk3288_grf->iomux_pwm1, IOMUX_PWM1);
assert((mv >= min_regulator_mv) && (mv <= max_regulator_mv));
duty_ns = (max_regulator_mv - mv) * period_ns /
(max_regulator_mv - min_regulator_mv);
pwm_init(1, period_ns, duty_ns);
}
static void configure_l2ctlr(void)
{
uint32_t l2ctlr;
l2ctlr = read_l2ctlr();
l2ctlr &= 0xfffc0000; /* clear bit0~bit17 */
/*
* Data RAM write latency: 2 cycles
* Data RAM read latency: 2 cycles
* Data RAM setup latency: 1 cycle
* Tag RAM write latency: 1 cycle
* Tag RAM read latency: 1 cycle
* Tag RAM setup latency: 1 cycle
*/
l2ctlr |= (1 << 3 | 1 << 0);
write_l2ctlr(l2ctlr);
}
void main(void)
{
#if CONFIG_COLLECT_TIMESTAMPS
uint64_t start_romstage_time;
uint64_t before_dram_time;
uint64_t after_dram_time;
uint64_t base_time = timestamp_get();
start_romstage_time = timestamp_get();
#endif
console_init();
configure_l2ctlr();
tsadc_init();
/* vdd_log 1200mv is enough for ddr run 666Mhz */
regulate_vdd_log(1200);
#if CONFIG_COLLECT_TIMESTAMPS
before_dram_time = timestamp_get();
#endif
sdram_init(get_sdram_config());
#if CONFIG_COLLECT_TIMESTAMPS
after_dram_time = timestamp_get();
#endif
/* Now that DRAM is up, add mappings for it and DMA coherency buffer. */
mmu_config_range((uintptr_t)_dram/MiB,
sdram_size_mb(), DCACHE_WRITEBACK);
mmu_config_range((uintptr_t)_dma_coherent/MiB,
_dma_coherent_size/MiB, DCACHE_OFF);
cbmem_initialize_empty();
#if CONFIG_COLLECT_TIMESTAMPS
timestamp_init(base_time);
timestamp_add(TS_START_ROMSTAGE, start_romstage_time);
timestamp_add(TS_BEFORE_INITRAM, before_dram_time);
timestamp_add(TS_AFTER_INITRAM, after_dram_time);
timestamp_add_now(TS_END_ROMSTAGE);
#endif
run_ramstage();
}

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src/mainboard/google/veyron_romy/sdram_configs.c Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc.
*/
#include <arch/io.h>
#include <boardid.h>
#include <console/console.h>
#include <gpio.h>
#include <soc/sdram.h>
#include <string.h>
#include <types.h>
static struct rk3288_sdram_params sdram_configs[] = {
#include "sdram_inf/sdram-lpddr3-samsung-2GB.inc" /* ram_code = 0000 */
#include "sdram_inf/sdram-lpddr3-hynix-2GB.inc" /* ram_code = 0001 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 0010 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 0011 */
#include "sdram_inf/sdram-ddr3-samsung-2GB.inc" /* ram_code = 0100 */
#include "sdram_inf/sdram-ddr3-hynix-2GB.inc" /* ram_code = 0101 */
#include "sdram_inf/sdram-ddr3-samsung-2GB.inc" /* ram_code = 0110 */
#include "sdram_inf/sdram-lpddr3-elpida-2GB.inc" /* ram_code = 0111 */
#include "sdram_inf/sdram-lpddr3-samsung-4GB.inc" /* ram_code = 1000 */
#include "sdram_inf/sdram-lpddr3-hynix-4GB.inc" /* ram_code = 1001 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 1010 */
#include "sdram_inf/sdram-lpddr3-elpida-4GB.inc" /* ram_code = 1011 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 1100 */
#include "sdram_inf/sdram-ddr3-hynix-2GB.inc" /* ram_code = 1101 */
#include "sdram_inf/sdram-ddr3-samsung-4GB.inc" /* ram_code = 1110 */
#include "sdram_inf/sdram-ddr3-hynix-4GB.inc" /* ram_code = 1111 */
};
const struct rk3288_sdram_params *get_sdram_config()
{
u32 ramcode = ram_code();
if (ramcode >= ARRAY_SIZE(sdram_configs)
|| sdram_configs[ramcode].dramtype == UNUSED)
die("Invalid RAMCODE.");
return &sdram_configs[ramcode];
}

78
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{
/* 4 Hynic H5TC4G63CFR(0101b) or H5TC4G63AFR(1101b) chips */
{
{
.rank = 0x1,
.col = 0xA,
.bk = 0x3,
.bw = 0x2,
.dbw = 0x1,
.row_3_4 = 0x0,
.cs0_row = 0xF,
.cs1_row = 0xF
},
{
.rank = 0x1,
.col = 0xA,
.bk = 0x3,
.bw = 0x2,
.dbw = 0x1,
.row_3_4 = 0x0,
.cs0_row = 0xF,
.cs1_row = 0xF
}
},
{
.togcnt1u = 0x29A,
.tinit = 0xC8,
.trsth = 0x1F4,
.togcnt100n = 0x42,
.trefi = 0x4E,
.tmrd = 0x4,
.trfc = 0xEA,
.trp = 0xA,
.trtw = 0x5,
.tal = 0x0,
.tcl = 0xA,
.tcwl = 0x7,
.tras = 0x19,
.trc = 0x24,
.trcd = 0xA,
.trrd = 0x7,
.trtp = 0x5,
.twr = 0xA,
.twtr = 0x5,
.texsr = 0x200,
.txp = 0x5,
.txpdll = 0x10,
.tzqcs = 0x40,
.tzqcsi = 0x0,
.tdqs = 0x1,
.tcksre = 0x7,
.tcksrx = 0x7,
.tcke = 0x4,
.tmod = 0xC,
.trstl = 0x43,
.tzqcl = 0x100,
.tmrr = 0x0,
.tckesr = 0x5,
.tdpd = 0x0
},
{
.dtpr0 = 0x48F9AAB4,
.dtpr1 = 0xEA0910,
.dtpr2 = 0x1002C200,
.mr[0] = 0xA60,
.mr[1] = 0x40,
.mr[2] = 0x10,
.mr[3] = 0x0
},
.noc_timing = 0x30B25564,
.noc_activate = 0x627,
.ddrconfig = 3,
.ddr_freq = 666*MHz,
.dramtype = DDR3,
.num_channels = 2,
.stride = 9,
.odt = 1
},

78
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{
/* 4 Hynix H5TC8G63xxx chips */
{
{
.rank = 0x2,
.col = 0xA,
.bk = 0x3,
.bw = 0x2,
.dbw = 0x1,
.row_3_4 = 0x0,
.cs0_row = 0xF,
.cs1_row = 0xF
},
{
.rank = 0x2,
.col = 0xA,
.bk = 0x3,
.bw = 0x2,
.dbw = 0x1,
.row_3_4 = 0x0,
.cs0_row = 0xF,
.cs1_row = 0xF
}
},
{
.togcnt1u = 0x29A,
.tinit = 0xC8,
.trsth = 0x1F4,
.togcnt100n = 0x42,
.trefi = 0x4E,
.tmrd = 0x4,
.trfc = 0xEA,
.trp = 0xA,
.trtw = 0x5,
.tal = 0x0,
.tcl = 0xA,
.tcwl = 0x7,
.tras = 0x19,
.trc = 0x24,
.trcd = 0xA,
.trrd = 0x7,
.trtp = 0x5,
.twr = 0xA,
.twtr = 0x5,
.texsr = 0x200,
.txp = 0x5,
.txpdll = 0x10,
.tzqcs = 0x40,
.tzqcsi = 0x0,
.tdqs = 0x1,
.tcksre = 0x7,
.tcksrx = 0x7,
.tcke = 0x4,
.tmod = 0xC,
.trstl = 0x43,
.tzqcl = 0x100,
.tmrr = 0x0,
.tckesr = 0x5,
.tdpd = 0x0
},
{
.dtpr0 = 0x48F9AAB4,
.dtpr1 = 0xEA0910,
.dtpr2 = 0x1002C200,
.mr[0] = 0xA60,
.mr[1] = 0x40,
.mr[2] = 0x10,
.mr[3] = 0x0
},
.noc_timing = 0x30B25564,
.noc_activate = 0x627,
.ddrconfig = 3,
.ddr_freq = 666*MHz,
.dramtype = DDR3,
.num_channels = 2,
.stride = 13,
.odt = 1
},

78
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{
/* two Samsung K4B4G1646D-BYK0 chips */
{
{
.rank = 0x1,
.col = 0xA,
.bk = 0x3,
.bw = 0x2,
.dbw = 0x1,
.row_3_4 = 0x0,
.cs0_row = 0xF,
.cs1_row = 0xF
},
{
.rank = 0x1,
.col = 0xA,
.bk = 0x3,
.bw = 0x2,
.dbw = 0x1,
.row_3_4 = 0x0,
.cs0_row = 0xF,
.cs1_row = 0xF
}
},
{
.togcnt1u = 0x29A,
.tinit = 0xC8,
.trsth = 0x1F4,
.togcnt100n = 0x42,
.trefi = 0x4E,
.tmrd = 0x4,
.trfc = 0xEA,
.trp = 0xA,
.trtw = 0x5,
.tal = 0x0,
.tcl = 0xA,
.tcwl = 0x7,
.tras = 0x19,
.trc = 0x24,
.trcd = 0xA,
.trrd = 0x7,
.trtp = 0x5,
.twr = 0xA,
.twtr = 0x5,
.texsr = 0x200,
.txp = 0x5,
.txpdll = 0x10,
.tzqcs = 0x40,
.tzqcsi = 0x0,
.tdqs = 0x1,
.tcksre = 0x7,
.tcksrx = 0x7,
.tcke = 0x4,
.tmod = 0xC,
.trstl = 0x43,
.tzqcl = 0x100,
.tmrr = 0x0,
.tckesr = 0x5,
.tdpd = 0x0
},
{
.dtpr0 = 0x48F9AAB4,
.dtpr1 = 0xEA0910,
.dtpr2 = 0x1002C200,
.mr[0] = 0xA60,
.mr[1] = 0x40,
.mr[2] = 0x10,
.mr[3] = 0x0
},
.noc_timing = 0x30B25564,
.noc_activate = 0x627,
.ddrconfig = 3,
.ddr_freq = 666*MHz,
.dramtype = DDR3,
.num_channels = 2,
.stride = 9,
.odt = 1
},

78
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{
/* 4 Samsung K4B8G1646Q chips */
{
{
.rank = 0x2,
.col = 0xA,
.bk = 0x3,
.bw = 0x2,
.dbw = 0x1,
.row_3_4 = 0x0,
.cs0_row = 0xF,
.cs1_row = 0xF
},
{
.rank = 0x2,
.col = 0xA,
.bk = 0x3,
.bw = 0x2,
.dbw = 0x1,
.row_3_4 = 0x0,
.cs0_row = 0xF,
.cs1_row = 0xF
}
},
{
.togcnt1u = 0x29A,
.tinit = 0xC8,
.trsth = 0x1F4,
.togcnt100n = 0x42,
.trefi = 0x4E,
.tmrd = 0x4,
.trfc = 0xEA,
.trp = 0xA,
.trtw = 0x5,
.tal = 0x0,
.tcl = 0xA,
.tcwl = 0x7,
.tras = 0x19,
.trc = 0x24,
.trcd = 0xA,
.trrd = 0x7,
.trtp = 0x5,
.twr = 0xA,
.twtr = 0x5,
.texsr = 0x200,
.txp = 0x5,
.txpdll = 0x10,
.tzqcs = 0x40,
.tzqcsi = 0x0,
.tdqs = 0x1,
.tcksre = 0x7,
.tcksrx = 0x7,
.tcke = 0x4,
.tmod = 0xC,
.trstl = 0x43,
.tzqcl = 0x100,
.tmrr = 0x0,
.tckesr = 0x5,
.tdpd = 0x0
},
{
.dtpr0 = 0x48F9AAB4,
.dtpr1 = 0xEA0910,
.dtpr2 = 0x1002C200,
.mr[0] = 0xA60,
.mr[1] = 0x40,
.mr[2] = 0x10,
.mr[3] = 0x0
},
.noc_timing = 0x30B25564,
.noc_activate = 0x627,
.ddrconfig = 3,
.ddr_freq = 666*MHz,
.dramtype = DDR3,
.num_channels = 2,
.stride = 13,
.odt = 1
},

78
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{
/* two ELPIDA F8132A3MA-GD-F chips */
{
{
.rank = 0x2,
.col = 0xA,
.bk = 0x3,
.bw = 0x2,
.dbw = 0x2,
.row_3_4 = 0x0,
.cs0_row = 0xE,
.cs1_row = 0xE
},
{
.rank = 0x2,
.col = 0xA,
.bk = 0x3,
.bw = 0x2,
.dbw = 0x2,
.row_3_4 = 0x0,
.cs0_row = 0xE,
.cs1_row = 0xE
}
},
{
.togcnt1u = 0x215,
.tinit = 0xC8,
.trsth = 0x0,
.togcnt100n = 0x35,
.trefi = 0x26,
.tmrd = 0x2,
.trfc = 0x70,
.trp = 0x2000D,
.trtw = 0x6,
.tal = 0x0,
.tcl = 0x8,
.tcwl = 0x4,
.tras = 0x17,
.trc = 0x24,
.trcd = 0xD,
.trrd = 0x6,
.trtp = 0x4,
.twr = 0x8,
.twtr = 0x4,
.texsr = 0x76,
.txp = 0x4,
.txpdll = 0x0,
.tzqcs = 0x30,
.tzqcsi = 0x0,
.tdqs = 0x1,
.tcksre = 0x2,
.tcksrx = 0x2,
.tcke = 0x4,
.tmod = 0x0,
.trstl = 0x0,
.tzqcl = 0xC0,
.tmrr = 0x4,
.tckesr = 0x8,
.tdpd = 0x1F4
},
{
.dtpr0 = 0x48D7DD93,
.dtpr1 = 0x187008D8,
.dtpr2 = 0x121076,
.mr[0] = 0x0,
.mr[1] = 0xC3,
.mr[2] = 0x6,
.mr[3] = 0x1
},
.noc_timing = 0x20D266A4,
.noc_activate = 0x5B6,
.ddrconfig = 2,
.ddr_freq = 533*MHz,
.dramtype = LPDDR3,
.num_channels = 2,
.stride = 9,
.odt = 0
},

78
src/mainboard/google/veyron_romy/sdram_inf/sdram-lpddr3-elpida-4GB.inc Normal file
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{
/* two ELPIDA FA232A2MA-GC-F chips */
{
{
.rank = 0x2,
.col = 0xB,
.bk = 0x3,
.bw = 0x2,
.dbw = 0x2,
.row_3_4 = 0x0,
.cs0_row = 0xE,
.cs1_row = 0xE
},
{
.rank = 0x2,
.col = 0xB,
.bk = 0x3,
.bw = 0x2,
.dbw = 0x2,
.row_3_4 = 0x0,
.cs0_row = 0xE,
.cs1_row = 0xE
}
},
{
.togcnt1u = 0x215,
.tinit = 0xC8,
.trsth = 0x0,
.togcnt100n = 0x35,
.trefi = 0x26,
.tmrd = 0x2,
.trfc = 0x70,
.trp = 0x2000D,
.trtw = 0x6,
.tal = 0x0,
.tcl = 0x8,
.tcwl = 0x4,
.tras = 0x17,
.trc = 0x24,
.trcd = 0xD,
.trrd = 0x6,
.trtp = 0x4,
.twr = 0x8,
.twtr = 0x4,
.texsr = 0x76,
.txp = 0x4,
.txpdll = 0x0,
.tzqcs = 0x30,
.tzqcsi = 0x0,
.tdqs = 0x1,
.tcksre = 0x2,
.tcksrx = 0x2,
.tcke = 0x4,
.tmod = 0x0,
.trstl = 0x0,
.tzqcl = 0xC0,
.tmrr = 0x4,
.tckesr = 0x8,
.tdpd = 0x1F4
},
{
.dtpr0 = 0x48D7DD93,
.dtpr1 = 0x187008D8,
.dtpr2 = 0x121076,
.mr[0] = 0x0,
.mr[1] = 0xC3,
.mr[2] = 0x6,
.mr[3] = 0x1
},
.noc_timing = 0x20D266A4,
.noc_activate = 0x5B6,
.ddrconfig = 6,
.ddr_freq = 533*MHz,
.dramtype = LPDDR3,
.num_channels = 2,
.stride = 13,
.odt = 0
},

78
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{
/* 2 Hynix H9CCNNN8GTMLAR chips */
{
{
.rank = 0x1,
.col = 0xA,
.bk = 0x3,
.bw = 0x2,
.dbw = 0x2,
.row_3_4 = 0x0,
.cs0_row = 0xF,
.cs1_row = 0xF
},
{
.rank = 0x1,
.col = 0xA,
.bk = 0x3,
.bw = 0x2,
.dbw = 0x2,
.row_3_4 = 0x0,
.cs0_row = 0xF,
.cs1_row = 0xF
}
},
{
.togcnt1u = 0x215,
.tinit = 0xC8,
.trsth = 0x0,
.togcnt100n = 0x35,
.trefi = 0x26,
.tmrd = 0x2,
.trfc = 0x70,
.trp = 0x2000D,
.trtw = 0x6,
.tal = 0x0,
.tcl = 0x8,
.tcwl = 0x4,
.tras = 0x17,
.trc = 0x24,
.trcd = 0xD,
.trrd = 0x6,
.trtp = 0x4,
.twr = 0x8,
.twtr = 0x4,
.texsr = 0x76,
.txp = 0x4,
.txpdll = 0x0,
.tzqcs = 0x30,
.tzqcsi = 0x0,
.tdqs = 0x1,
.tcksre = 0x2,
.tcksrx = 0x2,
.tcke = 0x4,
.tmod = 0x0,
.trstl = 0x0,
.tzqcl = 0xC0,
.tmrr = 0x4,
.tckesr = 0x8,
.tdpd = 0x1F4
},
{
.dtpr0 = 0x48D7DD93,
.dtpr1 = 0x187008D8,
.dtpr2 = 0x121076,
.mr[0] = 0x0,
.mr[1] = 0xC3,
.mr[2] = 0x6,
.mr[3] = 0x1
},
.noc_timing = 0x20D266A4,
.noc_activate = 0x5B6,
.ddrconfig = 14,
.ddr_freq = 533*MHz,
.dramtype = LPDDR3,
.num_channels = 2,
.stride = 9,
.odt = 0,
},

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{
{
{
.rank = 0x2,
.col = 0xA,
.bk = 0x3,
.bw = 0x2,
.dbw = 0x2,
.row_3_4 = 0x0,
.cs0_row = 0xF,
.cs1_row = 0xF
},
{
.rank = 0x2,
.col = 0xA,
.bk = 0x3,
.bw = 0x2,
.dbw = 0x2,
.row_3_4 = 0x0,
.cs0_row = 0xF,
.cs1_row = 0xF
}
},
{
.togcnt1u = 0x215,
.tinit = 0xC8,
.trsth = 0x0,
.togcnt100n = 0x35,
.trefi = 0x26,
.tmrd = 0x2,
.trfc = 0x70,
.trp = 0x2000D,
.trtw = 0x6,
.tal = 0x0,
.tcl = 0x8,
.tcwl = 0x4,
.tras = 0x17,
.trc = 0x24,
.trcd = 0xD,
.trrd = 0x6,
.trtp = 0x4,
.twr = 0x8,
.twtr = 0x4,
.texsr = 0x76,
.txp = 0x4,
.txpdll = 0x0,
.tzqcs = 0x30,
.tzqcsi = 0x0,
.tdqs = 0x1,
.tcksre = 0x2,
.tcksrx = 0x2,
.tcke = 0x4,
.tmod = 0x0,
.trstl = 0x0,
.tzqcl = 0xC0,
.tmrr = 0x4,
.tckesr = 0x8,
.tdpd = 0x1F4
},
{
.dtpr0 = 0x48D7DD93,
.dtpr1 = 0x187008D8,
.dtpr2 = 0x121076,
.mr[0] = 0x0,
.mr[1] = 0xC3,
.mr[2] = 0x6,
.mr[3] = 0x1
},
.noc_timing = 0x20D266A4,
.noc_activate = 0x5B6,
.ddrconfig = 3,
.ddr_freq = 533*MHz,
.dramtype = LPDDR3,
.num_channels = 2,
.stride = 13,
.odt = 0,
},

78
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{
/* two Samsung K4E8E304ED-EGCE000 chips */
{
{
.rank = 0x2,
.col = 0xA,
.bk = 0x3,
.bw = 0x2,
.dbw = 0x2,
.row_3_4 = 0x0,
.cs0_row = 0xE,
.cs1_row = 0xE
},
{
.rank = 0x2,
.col = 0xA,
.bk = 0x3,
.bw = 0x2,
.dbw = 0x2,
.row_3_4 = 0x0,
.cs0_row = 0xE,
.cs1_row = 0xE
}
},
{
.togcnt1u = 0x215,
.tinit = 0xC8,
.trsth = 0x0,
.togcnt100n = 0x35,
.trefi = 0x26,
.tmrd = 0x2,
.trfc = 0x70,
.trp = 0x2000D,
.trtw = 0x6,
.tal = 0x0,
.tcl = 0x8,
.tcwl = 0x4,
.tras = 0x17,
.trc = 0x24,
.trcd = 0xD,
.trrd = 0x6,
.trtp = 0x4,
.twr = 0x8,
.twtr = 0x4,
.texsr = 0x76,
.txp = 0x4,
.txpdll = 0x0,
.tzqcs = 0x30,
.tzqcsi = 0x0,
.tdqs = 0x1,
.tcksre = 0x2,
.tcksrx = 0x2,
.tcke = 0x4,
.tmod = 0x0,
.trstl = 0x0,
.tzqcl = 0xC0,
.tmrr = 0x4,
.tckesr = 0x8,
.tdpd = 0x1F4
},
{
.dtpr0 = 0x48D7DD93,
.dtpr1 = 0x187008D8,
.dtpr2 = 0x121076,
.mr[0] = 0x0,
.mr[1] = 0xC3,
.mr[2] = 0x6,
.mr[3] = 0x1
},
.noc_timing = 0x20D266A4,
.noc_activate = 0x5B6,
.ddrconfig = 2,
.ddr_freq = 533*MHz,
.dramtype = LPDDR3,
.num_channels = 2,
.stride = 9,
.odt = 0,
},

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{
{
{
.rank = 0x2,
.col = 0xB,
.bk = 0x3,
.bw = 0x2,
.dbw = 0x1,
.row_3_4 = 0x0,
.cs0_row = 0xE,
.cs1_row = 0xE
},
{
.rank = 0x2,
.col = 0xB,
.bk = 0x3,
.bw = 0x2,
.dbw = 0x1,
.row_3_4 = 0x0,
.cs0_row = 0xE,
.cs1_row = 0xE
}
},
{
.togcnt1u = 0x215,
.tinit = 0xC8,
.trsth = 0x0,
.togcnt100n = 0x35,
.trefi = 0x26,
.tmrd = 0x2,
.trfc = 0x70,
.trp = 0x2000D,
.trtw = 0x6,
.tal = 0x0,
.tcl = 0x8,
.tcwl = 0x4,
.tras = 0x17,
.trc = 0x24,
.trcd = 0xD,
.trrd = 0x6,
.trtp = 0x4,
.twr = 0x8,
.twtr = 0x4,
.texsr = 0x76,
.txp = 0x4,
.txpdll = 0x0,
.tzqcs = 0x30,
.tzqcsi = 0x0,
.tdqs = 0x1,
.tcksre = 0x2,
.tcksrx = 0x2,
.tcke = 0x4,
.tmod = 0x0,
.trstl = 0x0,
.tzqcl = 0xC0,
.tmrr = 0x4,
.tckesr = 0x8,
.tdpd = 0x1F4
},
{
.dtpr0 = 0x48D7DD93,
.dtpr1 = 0x187008D8,
.dtpr2 = 0x121076,
.mr[0] = 0x0,
.mr[1] = 0xC3,
.mr[2] = 0x6,
.mr[3] = 0x1
},
.noc_timing = 0x20D266A4,
.noc_activate = 0x5B6,
.ddrconfig = 6,
.ddr_freq = 533*MHz,
.dramtype = LPDDR3,
.num_channels = 2,
.stride = 13,
.odt = 0,
},

3
src/mainboard/google/veyron_romy/sdram_inf/sdram-unused.inc Normal file
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@ -0,0 +1,3 @@
{
.dramtype= UNUSED
},