util/inteltool: add Broadwell-U support
add handling of PCI IDs for Broadwell-U/Wildcat Point LP, using same functions as Haswell-U/Lynx Point LP Change-Id: I1094cbdace3c73f0f85c2e27c676b877b1a04bfe Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: http://review.coreboot.org/10209 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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@ -856,6 +856,7 @@ int print_gpios(struct pci_dev *sb, int show_all, int show_diffs)
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case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_FULL:
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case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_PREM:
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case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_BASE:
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case PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP:
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gpiobase = pci_read_word(sb, 0x48) & 0xfffc;
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gpio_registers = lynxpoint_lp_gpio_registers;
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size = ARRAY_SIZE(lynxpoint_lp_gpio_registers);
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@ -1050,6 +1051,7 @@ int print_gpios(struct pci_dev *sb, int show_all, int show_diffs)
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case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_FULL:
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case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_PREM:
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case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_BASE:
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case PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP:
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for (i = 0; i < 95; i++) {
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io_register_t tmp_gpio;
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char gpio_name[32];
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@ -84,6 +84,7 @@ static const struct {
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_M, "4th generation (Haswell family) Core Processor (Mobile)" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_E3, "4th generation (Haswell family) Core Processor (Xeon E3 v3)" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_U, "4th generation (Haswell family) Core Processor ULT" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_U, "5th generation (Broadwell family) Core Processor ULT" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL, "Bay Trail" },
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/* Southbridges (LPC controllers) */
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371XX, "371AB/EB/MB" },
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@ -163,6 +164,7 @@ static const struct {
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_FULL, "Lynx Point Low Power Full Featured Engineering Sample" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_PREM, "Lynx Point Low Power Premium SKU" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_BASE, "Lynx Point Low Power Base SKU" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP, "Wildcat Point Low Power SKU" },
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{ PCI_VENDOR_ID_INTEL, 0x2310, "DH89xxCC" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL_LPC, "Bay Trail" },
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};
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@ -112,6 +112,7 @@
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#define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_FULL 0x9c41
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#define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_PREM 0x9c43
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#define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_BASE 0x9c45
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#define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP 0x9cc5
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#define PCI_DEVICE_ID_INTEL_82810 0x7120
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#define PCI_DEVICE_ID_INTEL_82810_DC 0x7122
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#define PCI_DEVICE_ID_INTEL_82810E_DC 0x7124
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@ -173,6 +174,7 @@
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#define PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_M 0x0c04 /* Haswell (Mobile) */
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#define PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_E3 0x0c08 /* Haswell (Xeon E3 v3) */
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#define PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_U 0x0a04 /* Haswell-ULT */
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#define PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_U 0x1604 /* Broadwell-ULT */
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#define ARRAY_SIZE(a) ((int)(sizeof(a) / sizeof((a)[0])))
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@ -216,6 +216,7 @@ int print_mchbar(struct pci_dev *nb, struct pci_access *pacc)
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case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_M:
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case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_E3:
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case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_U:
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case PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_U:
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mchbar_phys = pci_read_long(nb, 0x48);
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mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32;
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mchbar_phys &= 0x0000007fffff8000UL; /* 38:15 */
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@ -216,6 +216,7 @@ int print_epbar(struct pci_dev *nb)
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case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_M:
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case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_E3:
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case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_U:
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case PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_U:
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epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe;
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epbar_phys |= ((uint64_t)pci_read_long(nb, 0x44)) << 32;
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break;
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@ -321,6 +322,7 @@ int print_dmibar(struct pci_dev *nb)
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dmibar_phys &= 0x0000007ffffff000UL; /* 38:12 */
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break;
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case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_U:
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case PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_U:
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dmi_registers = haswell_ult_dmi_registers;
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size = ARRAY_SIZE(haswell_ult_dmi_registers);
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dmibar_phys = pci_read_long(nb, 0x68);
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@ -418,6 +420,7 @@ int print_pciexbar(struct pci_dev *nb)
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case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_M:
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case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_E3:
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case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_U:
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case PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_U:
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pciexbar_reg = pci_read_long(nb, 0x60);
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pciexbar_reg |= ((uint64_t)pci_read_long(nb, 0x64)) << 32;
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break;
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@ -705,6 +705,7 @@ int print_pmbase(struct pci_dev *sb, struct pci_access *pacc)
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case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_FULL:
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case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_PREM:
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case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_BASE:
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case PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP:
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case PCI_DEVICE_ID_INTEL_BAYTRAIL_LPC:
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pmbase = pci_read_word(sb, 0x40) & 0xff80;
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pm_registers = pch_pm_registers;
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@ -98,6 +98,7 @@ int print_rcba(struct pci_dev *sb)
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case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_FULL:
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case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_PREM:
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case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_BASE:
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case PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP:
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rcba_phys = pci_read_long(sb, 0xf0) & 0xfffffffe;
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break;
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case PCI_DEVICE_ID_INTEL_ICH:
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@ -170,6 +170,7 @@ int print_spibar(struct pci_dev *sb) {
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case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_FULL:
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case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_PREM:
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case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_BASE:
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case PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP:
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rcba_phys = pci_read_long(sb, 0xf0) & 0xfffffffe;
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size = ARRAY_SIZE(spi_bar_registers);
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spi_register = spi_bar_registers;
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