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soc/intel/tigerlake: Configure FSP UPDs for minimum assertion widths 

Configure FSP UPDs for the chipset minimum assertion widths and
power cycle duration per mainboard variants.

* PchPmSlpS3MinAssert: SLP_S3 Minimum Assertion Width Policy
* PchPmSlpS4MinAssert: SLP_S4 Minimum Assertion Width Policy
* PchPmSlpSusMinAssert: SLP_SUS Minimum Assertion Width Policy
* PchPmSlpAMinAssert: SLP_A Minimum Assertion Width Policy
* PchPmPwrCycDur: PCH PM Reset Power Cycle Duration
* Check to avoid violating the PCH EDS recommendation for the
  PchPmPwrCycDur setting.

BUG=b:159108661

Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Change-Id: I8180d95a2185c3786334e10613f47e77b7bc9d5f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44557
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Jamie Ryu 2020-08-18 18:54:49 -07:00 committed by Tim Wawrzynczak
parent 81ab88b416
commit 5b7daa224c
2 changed files with 70 additions and 0 deletions
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53
src/soc/intel/tigerlake/chip.h
View File

@ -389,6 +389,59 @@ struct soc_intel_tigerlake_config {
* Default 0. Setting this to 1 to check CPU replacement. * Default 0. Setting this to 1 to check CPU replacement.
*/ */
uint8_t CpuReplacementCheck; uint8_t CpuReplacementCheck;
/*
* SLP_S3 Minimum Assertion Width Policy
* 1 = 60us
* 2 = 1ms
* 3 = 50ms (default)
* 4 = 2s
*/
uint8_t PchPmSlpS3MinAssert;
/*
* SLP_S4 Minimum Assertion Width Policy
* 1 = 1s (default)
* 2 = 2s
* 3 = 3s
* 4 = 4s
*/
uint8_t PchPmSlpS4MinAssert;
/*
* SLP_SUS Minimum Assertion Width Policy
* 1 = 0ms
* 2 = 500ms
* 3 = 1s
* 4 = 4s (default)
*/
uint8_t PchPmSlpSusMinAssert;
/*
* SLP_A Minimum Assertion Width Policy
* 1 = 0ms
* 2 = 4s
* 3 = 98ms
* 4 = 2s (default)
*/
uint8_t PchPmSlpAMinAssert;
/*
* PCH PM Reset Power Cycle Duration
* 0 = 4s (default)
* 1 = 1s
* 2 = 2s
* 3 = 3s
* 4 = 4s
*
* NOTE: Duration programmed in the PchPmPwrCycDur should never be smaller than the
* stretch duration programmed in the following registers:
* - GEN_PMCON_A.SLP_S3_MIN_ASST_WDTH (PchPmSlpS3MinAssert)
* - GEN_PMCON_A.S4MAW (PchPmSlpS4MinAssert)
* - PM_CFG.SLP_A_MIN_ASST_WDTH (PchPmSlpAMinAssert)
* - PM_CFG.SLP_LAN_MIN_ASST_WDTH
*/
uint8_t PchPmPwrCycDur;
}; };
typedef struct soc_intel_tigerlake_config config_t; typedef struct soc_intel_tigerlake_config config_t;

17
src/soc/intel/tigerlake/fsp_params.c
View File

@ -10,6 +10,7 @@
#include <intelblocks/cse.h> #include <intelblocks/cse.h>
#include <intelblocks/lpss.h> #include <intelblocks/lpss.h>
#include <intelblocks/mp_init.h> #include <intelblocks/mp_init.h>
#include <intelblocks/pmclib.h>
#include <intelblocks/xdci.h> #include <intelblocks/xdci.h>
#include <intelpch/lockdown.h> #include <intelpch/lockdown.h>
#include <security/vboot/vboot_common.h> #include <security/vboot/vboot_common.h>
@ -331,6 +332,22 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
} }
/* Apply minimum assertion width settings if non-zero */
if (config->PchPmSlpS3MinAssert)
params->PchPmSlpS3MinAssert = config->PchPmSlpS3MinAssert;
if (config->PchPmSlpS4MinAssert)
params->PchPmSlpS4MinAssert = config->PchPmSlpS4MinAssert;
if (config->PchPmSlpSusMinAssert)
params->PchPmSlpSusMinAssert = config->PchPmSlpSusMinAssert;
if (config->PchPmSlpAMinAssert)
params->PchPmSlpAMinAssert = config->PchPmSlpAMinAssert;
/* Set Power Cycle Duration */
if (config->PchPmPwrCycDur)
params->PchPmPwrCycDur = get_pm_pwr_cyc_dur(config->PchPmSlpS4MinAssert,
config->PchPmSlpS3MinAssert, config->PchPmSlpAMinAssert,
config->PchPmPwrCycDur);
/* EnableMultiPhaseSiliconInit for running MultiPhaseSiInit */ /* EnableMultiPhaseSiliconInit for running MultiPhaseSiInit */
params->EnableMultiPhaseSiliconInit = 1; params->EnableMultiPhaseSiliconInit = 1;
mainboard_silicon_init_params(params); mainboard_silicon_init_params(params);