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soc/amd/common: Correct SPI FIFO size check 

When checking that command and data fit in the FIFO, don't count the first
byte.  The command doesn't go through the FIFO.

TEST=confirm error (4+68>71) goes away on Mandolin
BUG=b:146225550

Change-Id: Ica2ca514deea401c9c5396913087e07a12ab3cf3
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37721
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Eric Peers <epeers@google.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Marshall Dawson 2019-12-13 17:32:53 -07:00 committed by Aaron Durbin
parent 92bc83674b
commit 5b9062f3f6
1 changed files with 2 additions and 1 deletions
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3
src/soc/amd/common/block/spi/fch_spi_flash.c
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@ -40,7 +40,8 @@ int fch_spi_flash_cmd_write(const u8 *cmd, size_t cmd_len, const void *data, siz
int ret;
u8 buff[SPI_FIFO_DEPTH + 1];
if ((cmd_len + data_len) > SPI_FIFO_DEPTH)
/* Ensure FIFO is large enough. First byte of command does not go in the FIFO. */
if ((cmd_len - 1 + data_len) > SPI_FIFO_DEPTH)
return -1;
memcpy(buff, cmd, cmd_len);
memcpy(buff + cmd_len, data, data_len);