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vendorcode/intel/FSP2_0/CPX-SP: update to ww36 

Intel CPX-SP FSP ww36 release has following changes:
* Update FSP header version to change among FSP releases.
* Add SPDRegVen field in memory map HOB, to facilitate SMBIOS type 11
(OEM strings) generation.

Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: I7a8dab3987c2f8f471b40f7b3b9ced0c2909271d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45100
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Jonathan Zhang 2020-09-03 14:31:37 -07:00 committed by Patrick Georgi
parent 27dd66aca7
commit 5bb89e7f0c
2 changed files with 11 additions and 8 deletions
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16
src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h
View File

@ -370,16 +370,18 @@ typedef struct {
**/
UINT32 mmiohBase;
/** Offset 0x0098 - High Gap
/** Offset 0x0098 - CPU Physical Address Limit
CPU Physical Address Limit
0:Disable, 1:Enable
**/
UINT8 CpuPaLimit;
/** Offset 0x0099 - High Gap
Enable or Disable High Gap
$EN_DIS
**/
UINT8 highGap;
/** Offset 0x0099
**/
UINT8 UnusedUpdSpace0;
/** Offset 0x009A - MMIO High Size
MMIO High Size, Number of 1GB contiguous regions to be assigned for MMIOH space
per CPU. Range 1-1024
@ -400,7 +402,7 @@ typedef struct {
/** Offset 0x009E
**/
UINT8 UnusedUpdSpace1[2];
UINT8 UnusedUpdSpace0[2];
/** Offset 0x00A0 - } TYPE:{Combo
Enable or Disable
@ -723,7 +725,7 @@ typedef struct {
/** Offset 0x015C
**/
UINT8 UnusedUpdSpace2[2];
UINT8 UnusedUpdSpace1[2];
/** Offset 0x015E
**/

3
src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h
View File

@ -45,6 +45,7 @@ are permitted provided that the following conditions are met:
#define MAX_IMC 2
#define MAX_CH 6
#define MC_MAX_NODE (MAX_SOCKET * MAX_IMC)
#define MAX_CHA_MAP 4
// Maximum KTI PORTS to be used in structure definition
#if (MAX_SOCKET == 1)
@ -154,7 +155,7 @@ typedef struct {
uint16_t M2PciePresentBitmap;
uint8_t TotM3Kti;
uint8_t TotCha;
uint32_t ChaList;
uint32_t ChaList[MAX_CHA_MAP];
uint32_t SocId;
QPI_PEER_DATA PeerInfo[MAX_FW_KTI_PORTS]; // QPI LEP info
} QPI_CPU_DATA;