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mb/google/brya: Enable eMMC HS400 mode for nissa 

Based on the nivviks and nereid schematics, nissa is using eMMC HS400
mode, so enable this in devicetree.

BUG=b:197479026
TEST=Build test nivviks and nereid

Signed-off-by: Reka Norman <rekanorman@google.com>
Change-Id: Ie9772385276d3629079b95024d3ffa04438f22c2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61998
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
This commit is contained in:
Reka Norman 2022-02-16 10:12:36 +11:00 committed by Felix Held
parent aade40c3f6
commit 5bba93e08a
1 changed files with 3 additions and 0 deletions
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3
src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb
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@ -17,6 +17,9 @@ chip soc/intel/alderlake
# Enable CNVi BT # Enable CNVi BT
register "CnviBtCore" = "true" register "CnviBtCore" = "true"
# eMMC HS400
register "emmc_enable_hs400_mode" = "1"
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C0 register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C0
register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C1 register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C1
register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # USB2_A0 register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # USB2_A0