cpu/intel: Refactor platform_enter_postcar()
There are benefits in placing the postcar_frame structure in .bss and returning control to romstage_main(). Change-Id: I0418a2abc74f749203c587b2763c5f8a5960e4f9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34808 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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5bc641afeb
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@ -22,6 +22,21 @@
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#define DCACHE_RAM_ROMSTAGE_STACK_SIZE 0x2000
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#define DCACHE_RAM_ROMSTAGE_STACK_SIZE 0x2000
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static struct postcar_frame early_mtrrs;
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/* prepare_and_run_postcar() determines the stack to use after
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* cache-as-ram is torn down as well as the MTRR settings to use. */
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static void prepare_and_run_postcar(struct postcar_frame *pcf)
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{
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if (postcar_frame_init(pcf, 0))
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die("Unable to initialize postcar frame.\n");
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fill_postcar_frame(pcf);
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run_postcar_phase(pcf);
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/* We do not return here. */
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}
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static void romstage_main(unsigned long bist)
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static void romstage_main(unsigned long bist)
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{
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{
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int i;
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int i;
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@ -52,7 +67,8 @@ static void romstage_main(unsigned long bist)
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printk(BIOS_DEBUG, "Smashed stack detected in romstage!\n");
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printk(BIOS_DEBUG, "Smashed stack detected in romstage!\n");
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}
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}
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platform_enter_postcar();
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prepare_and_run_postcar(&early_mtrrs);
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/* We do not return here. */
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}
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}
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#if !CONFIG(C_ENVIRONMENT_BOOTBLOCK)
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#if !CONFIG(C_ENVIRONMENT_BOOTBLOCK)
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@ -24,30 +24,23 @@
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#include <fsp/util.h>
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#include <fsp/util.h>
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#include <program_loading.h>
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#include <program_loading.h>
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/* platform_enter_postcar() determines the stack to use after
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void fill_postcar_frame(struct postcar_frame *pcf)
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* cache-as-ram is torn down as well as the MTRR settings to use,
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* and continues execution in postcar stage. */
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void platform_enter_postcar(void)
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{
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{
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struct postcar_frame pcf;
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uintptr_t top_of_ram;
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uintptr_t top_of_ram;
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if (postcar_frame_init(&pcf, 0))
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die("Unable to initialize postcar frame.\n");
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/* Cache the ROM as WP just below 4GiB. */
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/* Cache the ROM as WP just below 4GiB. */
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postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE,
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postcar_frame_add_mtrr(pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE,
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MTRR_TYPE_WRPROT);
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MTRR_TYPE_WRPROT);
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/* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
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/* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
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postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
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postcar_frame_add_mtrr(pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
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/* Cache at least 8 MiB below the top of ram, and at most 8 MiB
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/* Cache at least 8 MiB below the top of ram, and at most 8 MiB
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* above top of the ram. This satisfies MTRR alignment requirement
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* above top of the ram. This satisfies MTRR alignment requirement
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* with different TSEG size configurations. */
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* with different TSEG size configurations. */
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top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB);
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top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB);
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postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 16*MiB, MTRR_TYPE_WRBACK);
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postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 16*MiB, MTRR_TYPE_WRBACK);
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run_postcar_phase(&pcf);
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}
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}
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/* This is the romstage entry called from cpu/intel/car/romstage.c */
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/* This is the romstage entry called from cpu/intel/car/romstage.c */
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@ -5,6 +5,10 @@
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void mainboard_romstage_entry(unsigned long bist);
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void mainboard_romstage_entry(unsigned long bist);
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void platform_enter_postcar(void);
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/* fill_postcar_frame() is called after raminit completes and right before
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* calling run_postcar_phase(). Implementation should call postcar_frame_add_mtrr()
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* to tag memory ranges as cacheable to speed up execution of postcar and
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* early ramstage. */
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void fill_postcar_frame(struct postcar_frame *pcf);
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#endif /* _CPU_INTEL_ROMSTAGE_H */
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#endif /* _CPU_INTEL_ROMSTAGE_H */
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@ -43,17 +43,10 @@ void northbridge_write_smram(u8 smram)
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pci_write_config8(mch, SMRAMC, smram);
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pci_write_config8(mch, SMRAMC, smram);
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}
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}
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/* platform_enter_postcar() determines the stack to use after
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void fill_postcar_frame(struct postcar_frame *pcf)
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* cache-as-ram is torn down as well as the MTRR settings to use,
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* and continues execution in postcar stage. */
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void platform_enter_postcar(void)
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{
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{
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struct postcar_frame pcf;
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uintptr_t top_of_ram;
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uintptr_t top_of_ram;
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if (postcar_frame_init(&pcf, 0))
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die("Unable to initialize postcar frame.\n");
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/*
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/*
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* Choose to NOT set ROM as WP cacheable here.
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* Choose to NOT set ROM as WP cacheable here.
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* Timestamps indicate the CPU this northbridge code is
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* Timestamps indicate the CPU this northbridge code is
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@ -62,14 +55,10 @@ void platform_enter_postcar(void)
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*/
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*/
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/* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
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/* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
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postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
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postcar_frame_add_mtrr(pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
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/* Cache CBMEM region as WB. */
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/* Cache CBMEM region as WB. */
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top_of_ram = (uintptr_t)cbmem_top();
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top_of_ram = (uintptr_t)cbmem_top();
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postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 8*MiB,
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postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB,
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MTRR_TYPE_WRBACK);
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MTRR_TYPE_WRBACK);
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run_postcar_phase(&pcf);
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/* We do not return here. */
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}
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}
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@ -134,33 +134,24 @@ void stage_cache_external_region(void **base, size_t *size)
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+ northbridge_get_tseg_size() - CONFIG_SMM_RESERVED_SIZE);
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+ northbridge_get_tseg_size() - CONFIG_SMM_RESERVED_SIZE);
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}
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}
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/* platform_enter_postcar() determines the stack to use after
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void fill_postcar_frame(struct postcar_frame *pcf)
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* cache-as-ram is torn down as well as the MTRR settings to use,
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* and continues execution in postcar stage. */
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void platform_enter_postcar(void)
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{
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{
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struct postcar_frame pcf;
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uintptr_t top_of_ram;
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uintptr_t top_of_ram;
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if (postcar_frame_init(&pcf, 0))
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die("Unable to initialize postcar frame.\n");
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/* Cache the ROM as WP just below 4GiB. */
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/* Cache the ROM as WP just below 4GiB. */
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postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT);
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postcar_frame_add_romcache(pcf, MTRR_TYPE_WRPROT);
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/* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
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/* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
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postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
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postcar_frame_add_mtrr(pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
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/* Cache 8 MiB region below the top of ram and 2 MiB above top of
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/* Cache 8 MiB region below the top of ram and 2 MiB above top of
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* ram to cover both cbmem as the TSEG region.
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* ram to cover both cbmem as the TSEG region.
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*/
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*/
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top_of_ram = (uintptr_t)cbmem_top();
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top_of_ram = (uintptr_t)cbmem_top();
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postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 8*MiB,
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postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB,
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MTRR_TYPE_WRBACK);
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MTRR_TYPE_WRBACK);
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postcar_frame_add_mtrr(&pcf, northbridge_get_tseg_base(),
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postcar_frame_add_mtrr(pcf, northbridge_get_tseg_base(),
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northbridge_get_tseg_size(), MTRR_TYPE_WRBACK);
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northbridge_get_tseg_size(), MTRR_TYPE_WRBACK);
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run_postcar_phase(&pcf);
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/* We do not return here. */
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}
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}
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@ -53,29 +53,21 @@ void stage_cache_external_region(void **base, size_t *size)
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*base = (void *)((uint32_t)cbmem_top() + RESERVED_SMM_OFFSET);
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*base = (void *)((uint32_t)cbmem_top() + RESERVED_SMM_OFFSET);
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}
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}
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/* platform_enter_postcar() determines the stack to use after
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void fill_postcar_frame(struct postcar_frame *pcf)
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* cache-as-ram is torn down as well as the MTRR settings to use,
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* and continues execution in postcar stage. */
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void platform_enter_postcar(void)
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{
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{
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struct postcar_frame pcf;
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uintptr_t top_of_ram;
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uintptr_t top_of_ram;
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if (postcar_frame_init(&pcf, 0))
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die("Unable to initialize postcar frame.\n");
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/* Cache the ROM as WP just below 4GiB. */
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/* Cache the ROM as WP just below 4GiB. */
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postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT);
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postcar_frame_add_romcache(pcf, MTRR_TYPE_WRPROT);
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/* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
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/* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
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postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
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postcar_frame_add_mtrr(pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
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/* Cache at least 8 MiB below the top of ram, and at most 8 MiB
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/* Cache at least 8 MiB below the top of ram, and at most 8 MiB
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* above top of the ram. This satisfies MTRR alignment requirement
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* above top of the ram. This satisfies MTRR alignment requirement
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* with different TSEG size configurations.
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* with different TSEG size configurations.
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*/
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*/
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top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB);
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top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB);
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postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 16*MiB,
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postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 16*MiB,
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MTRR_TYPE_WRBACK);
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MTRR_TYPE_WRBACK);
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run_postcar_phase(&pcf);
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}
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}
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@ -68,27 +68,20 @@ void *cbmem_top(void)
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return (void *)tom;
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return (void *)tom;
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}
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}
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/* platform_enter_postcar() determines the stack to use after
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void fill_postcar_frame(struct postcar_frame *pcf)
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* cache-as-ram is torn down as well as the MTRR settings to use,
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* and continues execution in postcar stage. */
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void platform_enter_postcar(void)
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{
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{
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struct postcar_frame pcf;
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uintptr_t top_of_ram;
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uintptr_t top_of_ram;
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if (postcar_frame_init(&pcf, 0))
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die("Unable to initialize postcar frame.\n");
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/* Cache the ROM as WP just below 4GiB. */
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/* Cache the ROM as WP just below 4GiB. */
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postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT);
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postcar_frame_add_romcache(pcf, MTRR_TYPE_WRPROT);
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/* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
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/* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
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postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
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postcar_frame_add_mtrr(pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
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/* Cache CBMEM region as WB. */
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/* Cache CBMEM region as WB. */
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top_of_ram = (uintptr_t)cbmem_top();
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top_of_ram = (uintptr_t)cbmem_top();
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postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 8*MiB,
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postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB,
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MTRR_TYPE_WRBACK);
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MTRR_TYPE_WRBACK);
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run_postcar_phase(&pcf);
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}
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}
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+ northbridge_get_tseg_size() - CONFIG_SMM_RESERVED_SIZE);
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+ northbridge_get_tseg_size() - CONFIG_SMM_RESERVED_SIZE);
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}
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}
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/* platform_enter_postcar() determines the stack to use after
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void fill_postcar_frame(struct postcar_frame *pcf)
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* cache-as-ram is torn down as well as the MTRR settings to use,
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* and continues execution in postcar stage. */
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void platform_enter_postcar(void)
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{
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{
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struct postcar_frame pcf;
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uintptr_t top_of_ram;
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uintptr_t top_of_ram;
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if (postcar_frame_init(&pcf, 0))
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die("Unable to initialize postcar frame.\n");
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/* Cache the ROM as WP just below 4GiB. */
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/* Cache the ROM as WP just below 4GiB. */
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postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT);
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postcar_frame_add_romcache(pcf, MTRR_TYPE_WRPROT);
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/* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
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/* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
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postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
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postcar_frame_add_mtrr(pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
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/* Cache 8 MiB region below the top of ram and 2 MiB above top of
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/* Cache 8 MiB region below the top of ram and 2 MiB above top of
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* ram to cover both cbmem as the TSEG region.
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* ram to cover both cbmem as the TSEG region.
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*/
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*/
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top_of_ram = (uintptr_t)cbmem_top();
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top_of_ram = (uintptr_t)cbmem_top();
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postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 8*MiB,
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postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB,
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MTRR_TYPE_WRBACK);
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MTRR_TYPE_WRBACK);
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postcar_frame_add_mtrr(&pcf, northbridge_get_tseg_base(),
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postcar_frame_add_mtrr(pcf, northbridge_get_tseg_base(),
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northbridge_get_tseg_size(), MTRR_TYPE_WRBACK);
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northbridge_get_tseg_size(), MTRR_TYPE_WRBACK);
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run_postcar_phase(&pcf);
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/* We do not return here. */
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}
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}
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@ -58,32 +58,22 @@ void stage_cache_external_region(void **base, size_t *size)
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northbridge_get_tseg_size() - CONFIG_SMM_RESERVED_SIZE);
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northbridge_get_tseg_size() - CONFIG_SMM_RESERVED_SIZE);
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}
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}
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/* platform_enter_postcar() determines the stack to use after
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void fill_postcar_frame(struct postcar_frame *pcf)
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* cache-as-ram is torn down as well as the MTRR settings to use,
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* and continues execution in postcar stage. */
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void platform_enter_postcar(void)
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{
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{
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struct postcar_frame pcf;
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uintptr_t top_of_ram;
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uintptr_t top_of_ram;
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if (postcar_frame_init(&pcf, 0))
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die("Unable to initialize postcar frame.\n");
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/* Cache the ROM as WP just below 4GiB. */
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/* Cache the ROM as WP just below 4GiB. */
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postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT);
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postcar_frame_add_romcache(pcf, MTRR_TYPE_WRPROT);
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/* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
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/* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
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postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
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postcar_frame_add_mtrr(pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
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/* Cache at least 8 MiB below the top of ram, and at most 8 MiB
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/* Cache at least 8 MiB below the top of ram, and at most 8 MiB
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* above top of the ram. This satisfies MTRR alignment requirement
|
* above top of the ram. This satisfies MTRR alignment requirement
|
||||||
* with different TSEG size configurations.
|
* with different TSEG size configurations.
|
||||||
*/
|
*/
|
||||||
top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB);
|
top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB);
|
||||||
postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 8*MiB, MTRR_TYPE_WRBACK);
|
postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB, MTRR_TYPE_WRBACK);
|
||||||
postcar_frame_add_mtrr(&pcf, top_of_ram, 8*MiB, MTRR_TYPE_WRBACK);
|
postcar_frame_add_mtrr(pcf, top_of_ram, 8*MiB, MTRR_TYPE_WRBACK);
|
||||||
|
|
||||||
run_postcar_phase(&pcf);
|
|
||||||
|
|
||||||
/* We do not return here. */
|
|
||||||
}
|
}
|
||||||
|
|
|
@ -150,33 +150,23 @@ void stage_cache_external_region(void **base, size_t *size)
|
||||||
+ northbridge_get_tseg_size() - CONFIG_SMM_RESERVED_SIZE);
|
+ northbridge_get_tseg_size() - CONFIG_SMM_RESERVED_SIZE);
|
||||||
}
|
}
|
||||||
|
|
||||||
/* platform_enter_postcar() determines the stack to use after
|
void fill_postcar_frame(struct postcar_frame *pcf)
|
||||||
* cache-as-ram is torn down as well as the MTRR settings to use,
|
|
||||||
* and continues execution in postcar stage. */
|
|
||||||
void platform_enter_postcar(void)
|
|
||||||
{
|
{
|
||||||
struct postcar_frame pcf;
|
|
||||||
uintptr_t top_of_ram;
|
uintptr_t top_of_ram;
|
||||||
|
|
||||||
if (postcar_frame_init(&pcf, 0))
|
|
||||||
die("Unable to initialize postcar frame.\n");
|
|
||||||
|
|
||||||
/* Cache the ROM as WP just below 4GiB. */
|
/* Cache the ROM as WP just below 4GiB. */
|
||||||
postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT);
|
postcar_frame_add_romcache(pcf, MTRR_TYPE_WRPROT);
|
||||||
|
|
||||||
/* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
|
/* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
|
||||||
postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
|
postcar_frame_add_mtrr(pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
|
||||||
|
|
||||||
/* Cache 8 MiB region below the top of ram and 2 MiB above top of
|
/* Cache 8 MiB region below the top of ram and 2 MiB above top of
|
||||||
* ram to cover both cbmem as the TSEG region.
|
* ram to cover both cbmem as the TSEG region.
|
||||||
*/
|
*/
|
||||||
top_of_ram = (uintptr_t)cbmem_top();
|
top_of_ram = (uintptr_t)cbmem_top();
|
||||||
postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 8*MiB,
|
postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB,
|
||||||
MTRR_TYPE_WRBACK);
|
MTRR_TYPE_WRBACK);
|
||||||
postcar_frame_add_mtrr(&pcf, northbridge_get_tseg_base(),
|
postcar_frame_add_mtrr(pcf, northbridge_get_tseg_base(),
|
||||||
northbridge_get_tseg_size(), MTRR_TYPE_WRBACK);
|
northbridge_get_tseg_size(), MTRR_TYPE_WRBACK);
|
||||||
|
|
||||||
run_postcar_phase(&pcf);
|
|
||||||
|
|
||||||
/* We do not return here. */
|
|
||||||
}
|
}
|
||||||
|
|
|
@ -57,38 +57,28 @@ void stage_cache_external_region(void **base, size_t *size)
|
||||||
- CONFIG_IED_REGION_SIZE - CONFIG_SMM_RESERVED_SIZE);
|
- CONFIG_IED_REGION_SIZE - CONFIG_SMM_RESERVED_SIZE);
|
||||||
}
|
}
|
||||||
|
|
||||||
/* platform_enter_postcar() determines the stack to use after
|
void fill_postcar_frame(struct postcar_frame *pcf)
|
||||||
* cache-as-ram is torn down as well as the MTRR settings to use,
|
|
||||||
* and continues execution in postcar stage. */
|
|
||||||
void platform_enter_postcar(void)
|
|
||||||
{
|
{
|
||||||
struct postcar_frame pcf;
|
|
||||||
uintptr_t top_of_ram;
|
uintptr_t top_of_ram;
|
||||||
|
|
||||||
if (postcar_frame_init(&pcf, 0))
|
|
||||||
die("Unable to initialize postcar frame.\n");
|
|
||||||
|
|
||||||
/* Cache the ROM as WP just below 4GiB. */
|
/* Cache the ROM as WP just below 4GiB. */
|
||||||
postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT);
|
postcar_frame_add_romcache(pcf, MTRR_TYPE_WRPROT);
|
||||||
|
|
||||||
/* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
|
/* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
|
||||||
postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
|
postcar_frame_add_mtrr(pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
|
||||||
|
|
||||||
top_of_ram = (uintptr_t)cbmem_top();
|
top_of_ram = (uintptr_t)cbmem_top();
|
||||||
/* Cache 8MiB below the top of ram. On sandybridge systems the top of
|
/* Cache 8MiB below the top of ram. On sandybridge systems the top of
|
||||||
* ram under 4GiB is the start of the TSEG region. It is required to
|
* ram under 4GiB is the start of the TSEG region. It is required to
|
||||||
* be 8MiB aligned. Set this area as cacheable so it can be used later
|
* be 8MiB aligned. Set this area as cacheable so it can be used later
|
||||||
* for ramstage before setting up the entire RAM as cacheable. */
|
* for ramstage before setting up the entire RAM as cacheable. */
|
||||||
postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 8*MiB, MTRR_TYPE_WRBACK);
|
postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB, MTRR_TYPE_WRBACK);
|
||||||
|
|
||||||
/* Cache 8MiB at the top of ram. Top of ram on sandybridge systems
|
/* Cache 8MiB at the top of ram. Top of ram on sandybridge systems
|
||||||
* is where the TSEG region resides. However, it is not restricted
|
* is where the TSEG region resides. However, it is not restricted
|
||||||
* to SMM mode until SMM has been relocated. By setting the region
|
* to SMM mode until SMM has been relocated. By setting the region
|
||||||
* to cacheable it provides faster access when relocating the SMM
|
* to cacheable it provides faster access when relocating the SMM
|
||||||
* handler as well as using the TSEG region for other purposes. */
|
* handler as well as using the TSEG region for other purposes. */
|
||||||
postcar_frame_add_mtrr(&pcf, top_of_ram, 8*MiB, MTRR_TYPE_WRBACK);
|
postcar_frame_add_mtrr(pcf, top_of_ram, 8*MiB, MTRR_TYPE_WRBACK);
|
||||||
|
|
||||||
run_postcar_phase(&pcf);
|
|
||||||
|
|
||||||
/* We do not return here. */
|
|
||||||
}
|
}
|
||||||
|
|
|
@ -145,33 +145,23 @@ void stage_cache_external_region(void **base, size_t *size)
|
||||||
+ northbridge_get_tseg_size() - CONFIG_SMM_RESERVED_SIZE);
|
+ northbridge_get_tseg_size() - CONFIG_SMM_RESERVED_SIZE);
|
||||||
}
|
}
|
||||||
|
|
||||||
/* platform_enter_postcar() determines the stack to use after
|
void fill_postcar_frame(struct postcar_frame *pcf)
|
||||||
* cache-as-ram is torn down as well as the MTRR settings to use,
|
|
||||||
* and continues execution in postcar stage. */
|
|
||||||
void platform_enter_postcar(void)
|
|
||||||
{
|
{
|
||||||
struct postcar_frame pcf;
|
|
||||||
uintptr_t top_of_ram;
|
uintptr_t top_of_ram;
|
||||||
|
|
||||||
if (postcar_frame_init(&pcf, 0))
|
|
||||||
die("Unable to initialize postcar frame.\n");
|
|
||||||
|
|
||||||
/* Cache the ROM as WP just below 4GiB. */
|
/* Cache the ROM as WP just below 4GiB. */
|
||||||
postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT);
|
postcar_frame_add_romcache(pcf, MTRR_TYPE_WRPROT);
|
||||||
|
|
||||||
/* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
|
/* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
|
||||||
postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
|
postcar_frame_add_mtrr(pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
|
||||||
|
|
||||||
/* Cache 8 MiB region below the top of ram and 2 MiB above top of
|
/* Cache 8 MiB region below the top of ram and 2 MiB above top of
|
||||||
* ram to cover both cbmem as the TSEG region.
|
* ram to cover both cbmem as the TSEG region.
|
||||||
*/
|
*/
|
||||||
top_of_ram = (uintptr_t)cbmem_top();
|
top_of_ram = (uintptr_t)cbmem_top();
|
||||||
postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 8*MiB,
|
postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB,
|
||||||
MTRR_TYPE_WRBACK);
|
MTRR_TYPE_WRBACK);
|
||||||
postcar_frame_add_mtrr(&pcf, northbridge_get_tseg_base(),
|
postcar_frame_add_mtrr(pcf, northbridge_get_tseg_base(),
|
||||||
northbridge_get_tseg_size(), MTRR_TYPE_WRBACK);
|
northbridge_get_tseg_size(), MTRR_TYPE_WRBACK);
|
||||||
|
|
||||||
run_postcar_phase(&pcf);
|
|
||||||
|
|
||||||
/* We do not return here. */
|
|
||||||
}
|
}
|
||||||
|
|
|
@ -49,7 +49,22 @@
|
||||||
* Because we can't use global variables the stack is used for allocations --
|
* Because we can't use global variables the stack is used for allocations --
|
||||||
* thus the need to call back and forth. */
|
* thus the need to call back and forth. */
|
||||||
|
|
||||||
static void platform_enter_postcar(void);
|
static struct postcar_frame early_mtrrs;
|
||||||
|
|
||||||
|
static void fill_postcar_frame(struct postcar_frame *pcf);
|
||||||
|
|
||||||
|
/* prepare_and_run_postcar() determines the stack to use after
|
||||||
|
* cache-as-ram is torn down as well as the MTRR settings to use. */
|
||||||
|
static void prepare_and_run_postcar(struct postcar_frame *pcf)
|
||||||
|
{
|
||||||
|
if (postcar_frame_init(pcf, 0))
|
||||||
|
die("Unable to initialize postcar frame.\n");
|
||||||
|
|
||||||
|
fill_postcar_frame(pcf);
|
||||||
|
|
||||||
|
run_postcar_phase(pcf);
|
||||||
|
/* We do not return here. */
|
||||||
|
}
|
||||||
|
|
||||||
static void program_base_addresses(void)
|
static void program_base_addresses(void)
|
||||||
{
|
{
|
||||||
|
@ -129,9 +144,8 @@ static void romstage_main(uint64_t tsc, uint32_t bist)
|
||||||
/* Call into mainboard. */
|
/* Call into mainboard. */
|
||||||
mainboard_romstage_entry(&rp);
|
mainboard_romstage_entry(&rp);
|
||||||
|
|
||||||
platform_enter_postcar();
|
prepare_and_run_postcar(&early_mtrrs);
|
||||||
|
/* We do not return here. */
|
||||||
/* We don't return here */
|
|
||||||
}
|
}
|
||||||
|
|
||||||
/* This wrapper enables easy transition towards C_ENVIRONMENT_BOOTBLOCK,
|
/* This wrapper enables easy transition towards C_ENVIRONMENT_BOOTBLOCK,
|
||||||
|
@ -238,28 +252,21 @@ void romstage_common(struct romstage_params *params)
|
||||||
romstage_handoff_init(prev_sleep_state == ACPI_S3);
|
romstage_handoff_init(prev_sleep_state == ACPI_S3);
|
||||||
}
|
}
|
||||||
|
|
||||||
/* setup_stack_and_mtrrs() determines the stack to use after
|
static void fill_postcar_frame(struct postcar_frame *pcf)
|
||||||
* cache-as-ram is torn down as well as the MTRR settings to use. */
|
|
||||||
static void platform_enter_postcar(void)
|
|
||||||
{
|
{
|
||||||
struct postcar_frame pcf;
|
|
||||||
uintptr_t top_of_ram;
|
uintptr_t top_of_ram;
|
||||||
|
|
||||||
if (postcar_frame_init(&pcf, 0))
|
|
||||||
die("Unable to initialize postcar frame.\n");
|
|
||||||
/* Cache the ROM as WP just below 4GiB. */
|
/* Cache the ROM as WP just below 4GiB. */
|
||||||
postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT);
|
postcar_frame_add_romcache(pcf, MTRR_TYPE_WRPROT);
|
||||||
|
|
||||||
/* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
|
/* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
|
||||||
postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
|
postcar_frame_add_mtrr(pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
|
||||||
|
|
||||||
/* Cache at least 8 MiB below the top of ram, and at most 8 MiB
|
/* Cache at least 8 MiB below the top of ram, and at most 8 MiB
|
||||||
* above top of the ram. This satisfies MTRR alignment requirement
|
* above top of the ram. This satisfies MTRR alignment requirement
|
||||||
* with different TSEG size configurations.
|
* with different TSEG size configurations.
|
||||||
*/
|
*/
|
||||||
top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB);
|
top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB);
|
||||||
postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 16*MiB,
|
postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 16*MiB,
|
||||||
MTRR_TYPE_WRBACK);
|
MTRR_TYPE_WRBACK);
|
||||||
|
|
||||||
run_postcar_phase(&pcf);
|
|
||||||
}
|
}
|
||||||
|
|
|
@ -35,31 +35,23 @@
|
||||||
#include <soc/romstage.h>
|
#include <soc/romstage.h>
|
||||||
#include <soc/spi.h>
|
#include <soc/spi.h>
|
||||||
|
|
||||||
/* platform_enter_postcar() determines the stack to use after
|
void fill_postcar_frame(struct postcar_frame *pcf)
|
||||||
* cache-as-ram is torn down as well as the MTRR settings to use,
|
|
||||||
* and continues execution in postcar stage. */
|
|
||||||
void platform_enter_postcar(void)
|
|
||||||
{
|
{
|
||||||
struct postcar_frame pcf;
|
|
||||||
uintptr_t top_of_ram;
|
uintptr_t top_of_ram;
|
||||||
|
|
||||||
if (postcar_frame_init(&pcf, 0))
|
|
||||||
die("Unable to initialize postcar frame.\n");
|
|
||||||
/* Cache the ROM as WP just below 4GiB. */
|
/* Cache the ROM as WP just below 4GiB. */
|
||||||
postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT);
|
postcar_frame_add_romcache(pcf, MTRR_TYPE_WRPROT);
|
||||||
|
|
||||||
/* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
|
/* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
|
||||||
postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
|
postcar_frame_add_mtrr(pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
|
||||||
|
|
||||||
/* Cache at least 8 MiB below the top of ram, and at most 8 MiB
|
/* Cache at least 8 MiB below the top of ram, and at most 8 MiB
|
||||||
* above top of the ram. This satisfies MTRR alignment requirement
|
* above top of the ram. This satisfies MTRR alignment requirement
|
||||||
* with different TSEG size configurations.
|
* with different TSEG size configurations.
|
||||||
*/
|
*/
|
||||||
top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB);
|
top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB);
|
||||||
postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 16*MiB,
|
postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 16*MiB,
|
||||||
MTRR_TYPE_WRBACK);
|
MTRR_TYPE_WRBACK);
|
||||||
|
|
||||||
run_postcar_phase(&pcf);
|
|
||||||
}
|
}
|
||||||
|
|
||||||
/* Entry from cpu/intel/car/romstage.c. */
|
/* Entry from cpu/intel/car/romstage.c. */
|
||||||
|
|
Loading…
Reference in New Issue