GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Do sdram setup for fixed memory sizes. This really only works on 

embedded boards that have fixed memory configuration.


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1240 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Greg Watson 2003-11-02 16:59:24 +00:00
parent 6f2e86d278
commit 5bcd408b8e
1 changed files with 22 additions and 196 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

218
src/cpu/ppc/ppc4xx/sdram.c
View File

@ -24,31 +24,14 @@
#include <ppc_asm.tmpl>
#include <ppc.h>
#include <ppc4xx.h>
#include <timer.h>
#include <clock.h>
#define CONFIG_SDRAM_BANK0
#ifdef CONFIG_SDRAM_BANK0
#define MAGIC0 0x00000000
#define MAGIC1 0x11111111
#define MAGIC2 0x22222222
#define MAGIC3 0x33333333
#define MAGIC4 0x44444444
#define MAGIC5 0x55555555
#define MAGIC6 0x66666666
#define ADDR_ZERO 0x00000000
#define ADDR_400 0x00000400
#define ADDR_01MB 0x00100000
#define ADDR_08MB 0x00800000
#define ADDR_16MB 0x01000000
#define ADDR_32MB 0x02000000
#define ADDR_64MB 0x04000000
#define ADDR_128MB 0x08000000
#define mtsdram0(reg, data) mtdcr(memcfga,reg);mtdcr(memcfgd,data)
/*-----------------------------------------------------------------------
*/
void sdram_init(void)
@ -60,7 +43,7 @@ void sdram_init(void)
/*
* Determine SDRAM speed
*/
speed = get_bus_freq(0); /* parameter not used on ppc4xx */
speed = get_bus_freq(); /* parameter not used on ppc4xx */
/*
* Support for 100MHz and 133MHz SDRAM
@ -79,6 +62,13 @@ void sdram_init(void)
rtr = 0x05f00000;
}
/*
* Disable memory controller.
*/
/* TODO: work out why this trashes cache ram */
//mtsdram0(mem_mcopt1, 0x00000000);
#if EMBEDDED_RAM_SIZE==128*1024*1024
/*
* Set MB0CF for bank 0. (0-128MB) Address Mode 3 since 13x10(4)
*/
@ -86,52 +76,7 @@ void sdram_init(void)
mtsdram0(mem_sdtr1, sdtr1);
mtsdram0(mem_rtr, rtr);
/*
* Wait for 200us
*/
udelay(200);
/*
* Set memory controller options reg, MCOPT1.
* Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst
* read/prefetch.
*/
mtsdram0(mem_mcopt1, 0x80800000);
/*
* Wait for 10ms
*/
udelay(10000);
/*
* Test if 128 MByte are equipped (mirror test)
*/
*(volatile unsigned long *)ADDR_ZERO = MAGIC0;
*(volatile unsigned long *)ADDR_08MB = MAGIC1;
*(volatile unsigned long *)ADDR_16MB = MAGIC2;
*(volatile unsigned long *)ADDR_32MB = MAGIC3;
*(volatile unsigned long *)ADDR_64MB = MAGIC4;
if ((*(volatile unsigned long *)ADDR_ZERO == MAGIC0) &&
(*(volatile unsigned long *)ADDR_08MB == MAGIC1) &&
(*(volatile unsigned long *)ADDR_16MB == MAGIC2) &&
(*(volatile unsigned long *)ADDR_32MB == MAGIC3)) {
/*
* OK, 128MB detected -> all done
*/
return;
}
/*
* Now test for 64 MByte...
*/
/*
* Disable memory controller.
*/
mtsdram0(mem_mcopt1, 0x00000000);
#elif EMBEDDED_RAM_SIZE==64*1024*1024
/*
* Set MB0CF for bank 0. (0-64MB) Address Mode 3 since 13x9(4)
*/
@ -139,6 +84,17 @@ void sdram_init(void)
mtsdram0(mem_sdtr1, sdtr1);
mtsdram0(mem_rtr, rtr);
#elif EMBEDDED_RAM_SIZE==32*1024*1024
/*
* Set MB0CF for bank 0. (0-32MB) Address Mode 2 since 12x9(4)
*/
mtsdram0(mem_mb0cf, 0x00062001);
#elif EMBEDDED_RAM_SIZE==16*1024*1024
/*
* Set MB0CF for bank 0. (0-16MB) Address Mode 4 since 12x8(4)
*/
mtsdram0(mem_mb0cf, 0x00046001);
#endif
/*
* Wait for 200us
@ -156,136 +112,6 @@ void sdram_init(void)
* Wait for 10ms
*/
udelay(10000);
/*
* Test if 64 MByte are equipped (mirror test)
*/
*(volatile unsigned long *)ADDR_ZERO = MAGIC0;
*(volatile unsigned long *)ADDR_08MB = MAGIC1;
*(volatile unsigned long *)ADDR_16MB = MAGIC2;
*(volatile unsigned long *)ADDR_32MB = MAGIC3;
if ((*(volatile unsigned long *)ADDR_ZERO == MAGIC0) &&
(*(volatile unsigned long *)ADDR_08MB == MAGIC1) &&
(*(volatile unsigned long *)ADDR_16MB == MAGIC2)) {
/*
* OK, 64MB detected -> all done
*/
return;
}
/*
* Now test for 32 MByte...
*/
/*
* Disable memory controller.
*/
mtsdram0(mem_mcopt1, 0x00000000);
/*
* Set MB0CF for bank 0. (0-32MB) Address Mode 2 since 12x9(4)
*/
mtsdram0(mem_mb0cf, 0x00062001);
/*
* Set memory controller options reg, MCOPT1.
* Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst
* read/prefetch.
*/
mtsdram0(mem_mcopt1, 0x80800000);
/*
* Wait for 10ms
*/
udelay(10000);
/*
* Test if 32 MByte are equipped (mirror test)
*/
*(volatile unsigned long *)ADDR_ZERO = MAGIC0;
*(volatile unsigned long *)ADDR_400 = MAGIC1;
*(volatile unsigned long *)ADDR_08MB = MAGIC2;
*(volatile unsigned long *)ADDR_16MB = MAGIC3;
if ((*(volatile unsigned long *)ADDR_ZERO == MAGIC0) &&
(*(volatile unsigned long *)ADDR_400 == MAGIC1) &&
(*(volatile unsigned long *)ADDR_08MB == MAGIC2)) {
/*
* OK, 32MB detected -> all done
*/
return;
}
/*
* Now test for 16 MByte...
*/
/*
* Disable memory controller.
*/
mtsdram0(mem_mcopt1, 0x00000000);
/*
* Set MB0CF for bank 0. (0-16MB) Address Mode 4 since 12x8(4)
*/
mtsdram0(mem_mb0cf, 0x00046001);
/*
* Set memory controller options reg, MCOPT1.
* Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst
* read/prefetch.
*/
mtsdram0(mem_mcopt1, 0x80800000);
/*
* Wait for 10ms
*/
udelay(10000);
/*
* Test if 16 MByte are equipped (mirror test)
*/
*(volatile unsigned long *)ADDR_ZERO = MAGIC0;
*(volatile unsigned long *)ADDR_400 = MAGIC1;
*(volatile unsigned long *)ADDR_01MB = MAGIC5;
*(volatile unsigned long *)ADDR_08MB = MAGIC2;
/* *(volatile unsigned long *)ADDR_16MB = MAGIC3;*/
if ((*(volatile unsigned long *)ADDR_ZERO == MAGIC0) &&
(*(volatile unsigned long *)ADDR_400 == MAGIC1) &&
(*(volatile unsigned long *)ADDR_01MB == MAGIC5) &&
(*(volatile unsigned long *)ADDR_08MB == MAGIC2)) {
/*
* OK, 16MB detected -> all done
*/
return;
}
/*
* Setup for 4 MByte...
*/
/*
* Disable memory controller.
*/
mtsdram0(mem_mcopt1, 0x00000000);
/*
* Set MB0CF for bank 0. (0-4MB) Address Mode 5 since 11x8(2)
*/
mtsdram0(mem_mb0cf, 0x00008001);
/*
* Set memory controller options reg, MCOPT1.
* Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst
* read/prefetch.
*/
mtsdram0(mem_mcopt1, 0x80800000);
/*
* Wait for 10ms
*/
udelay(10000);
}
#endif /* CONFIG_SDRAM_BANK0 */