Clean up some comments and white space in gx2/northbridgeinit.c
and gx2/raminit.c. This is Abuild and boot tested. Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6014 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Nils Jacobs
Uwe Hermann
parent
b54585244b
commit
5beac7f996
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@ -22,26 +22,25 @@ struct gliutable {
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};
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struct gliutable gliu0table[] = {
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{.desc_name=MSR_GLIU0_BASE1, .desc_type= BM,.hi= MSR_MC + 0x0,.lo= 0x0FFF80}, /* 0-7FFFF to MC*/
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{.desc_name=MSR_GLIU0_BASE2, .desc_type= BM,.hi= MSR_MC + 0x0,.lo=(0x80 << 20) + 0x0FFFE0}, /* 80000-9ffff to Mc*/
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{.desc_name=MSR_GLIU0_SHADOW, .desc_type= SC_SHADOW,.hi= MSR_MC + 0x0,.lo= 0x03}, /* C0000-Fffff split to MC and PCI (sub decode) A0000-Bffff handled by SoftVideo*/
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{.desc_name=MSR_GLIU0_SYSMEM, .desc_type= R_SYSMEM,.hi= MSR_MC,.lo= 0x0}, /* Catch and fix dynamicly.*/
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{.desc_name=MSR_GLIU0_DMM, .desc_type= BMO_DMM,.hi= MSR_MC,.lo= 0x0}, /* Catch and fix dynamicly.*/
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{.desc_name=MSR_GLIU0_SMM, .desc_type= BMO_SMM,.hi= MSR_MC,.lo= 0x0}, /* Catch and fix dynamicly.*/
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{.desc_name=MSR_GLIU0_BASE1, .desc_type= BM,.hi= MSR_MC + 0x0,.lo= 0x0FFF80}, /* 0-7FFFF to MC */
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{.desc_name=MSR_GLIU0_BASE2, .desc_type= BM,.hi= MSR_MC + 0x0,.lo=(0x80 << 20) + 0x0FFFE0}, /* 80000-9ffff to Mc */
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{.desc_name=MSR_GLIU0_SHADOW, .desc_type= SC_SHADOW,.hi= MSR_MC + 0x0,.lo= 0x03}, /* C0000-Fffff split to MC and PCI (sub decode) A0000-Bffff handled by SoftVideo */
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{.desc_name=MSR_GLIU0_SYSMEM, .desc_type= R_SYSMEM,.hi= MSR_MC,.lo= 0x0}, /* Catch and fix dynamicly. */
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{.desc_name=MSR_GLIU0_DMM, .desc_type= BMO_DMM,.hi= MSR_MC,.lo= 0x0}, /* Catch and fix dynamicly. */
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{.desc_name=MSR_GLIU0_SMM, .desc_type= BMO_SMM,.hi= MSR_MC,.lo= 0x0}, /* Catch and fix dynamicly. */
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{.desc_name=GLIU0_GLD_MSR_COH,.desc_type= OTHER,.hi= 0x0,.lo= GL0_CPU},
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{.desc_name=GL_END, .desc_type= GL_END,.hi= 0x0,.lo= 0x0},
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};
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struct gliutable gliu1table[] = {
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{.desc_name=MSR_GLIU1_BASE1,.desc_type= BM,.hi= MSR_GL0 + 0x0,.lo= 0x0FFF80}, /* 0-7FFFF to MC*/
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{.desc_name=MSR_GLIU1_BASE2,.desc_type= BM,.hi= MSR_GL0 + 0x0,.lo= (0x80 << 20) +0x0FFFE0}, /* 80000-9ffff to Mc*/
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{.desc_name=MSR_GLIU1_SHADOW,.desc_type= SC_SHADOW,.hi= MSR_GL0 + 0x0,.lo= 0x03}, /* C0000-Fffff split to MC and PCI (sub decode)*/
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{.desc_name=MSR_GLIU1_SYSMEM,.desc_type= R_SYSMEM,.hi= MSR_GL0,.lo= 0x0}, /* Catch and fix dynamicly.*/
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{.desc_name=MSR_GLIU1_DMM,.desc_type= BM_DMM,.hi= MSR_GL0,.lo= 0x0}, /* Catch and fix dynamicly.*/
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{.desc_name=MSR_GLIU1_SMM,.desc_type= BM_SMM,.hi= MSR_GL0,.lo= 0x0}, /* Catch and fix dynamicly.*/
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{.desc_name=MSR_GLIU1_BASE1,.desc_type= BM,.hi= MSR_GL0 + 0x0,.lo= 0x0FFF80}, /* 0-7FFFF to MC */
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{.desc_name=MSR_GLIU1_BASE2,.desc_type= BM,.hi= MSR_GL0 + 0x0,.lo= (0x80 << 20) +0x0FFFE0}, /* 80000-9ffff to Mc */
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{.desc_name=MSR_GLIU1_SHADOW,.desc_type= SC_SHADOW,.hi= MSR_GL0 + 0x0,.lo= 0x03}, /* C0000-Fffff split to MC and PCI (sub decode) */
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{.desc_name=MSR_GLIU1_SYSMEM,.desc_type= R_SYSMEM,.hi= MSR_GL0,.lo= 0x0}, /* Catch and fix dynamicly. */
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{.desc_name=MSR_GLIU1_DMM,.desc_type= BM_DMM,.hi= MSR_GL0,.lo= 0x0}, /* Catch and fix dynamicly. */
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{.desc_name=MSR_GLIU1_SMM,.desc_type= BM_SMM,.hi= MSR_GL0,.lo= 0x0}, /* Catch and fix dynamicly. */
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{.desc_name=GLIU1_GLD_MSR_COH,.desc_type= OTHER,.hi= 0x0,.lo= GL1_GLIU0},
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{.desc_name=MSR_GLIU1_FPU_TRAP,.desc_type= SCIO,.hi= (GL1_GLCP << 29) + 0x0,.lo= 0x033000F0}, /* FooGlue FPU 0xF0*/
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{.desc_name=MSR_GLIU1_FPU_TRAP,.desc_type= SCIO,.hi= (GL1_GLCP << 29) + 0x0,.lo= 0x033000F0}, /* FooGlue FPU 0xF0 */
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{.desc_name=GL_END,.desc_type= GL_END,.hi= 0x0,.lo= 0x0},
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};
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@ -54,18 +53,18 @@ struct msrinit {
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struct msrinit ClockGatingDefault [] = {
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{GLIU0_GLD_MSR_PM, {.hi=0x00,.lo=0x0005}},
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/* MC must stay off in SDR mode. It is turned on in CPUBug??? lotus #77.142*/
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/* MC must stay off in SDR mode. It is turned on in CPUBug??? lotus #77.142 */
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{MC_GLD_MSR_PM, {.hi=0x00,.lo=0x0000}},
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{GLIU1_GLD_MSR_PM, {.hi=0x00,.lo=0x0005}},
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{VG_GLD_MSR_PM, {.hi=0x00,.lo=0x0000}}, /* lotus #77.163*/
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{VG_GLD_MSR_PM, {.hi=0x00,.lo=0x0000}}, /* lotus #77.163 */
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{GP_GLD_MSR_PM, {.hi=0x00,.lo=0x0001}},
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{DF_GLD_MSR_PM, {.hi=0x00,.lo=0x0155}},
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{GLCP_GLD_MSR_PM, {.hi=0x00,.lo=0x0015}},
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{GLPCI_GLD_MSR_PM, {.hi=0x00,.lo=0x0015}},
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{FG_GLD_MSR_PM, {.hi=0x00,.lo=0x0000}}, /* Always on*/
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{FG_GLD_MSR_PM, {.hi=0x00,.lo=0x0000}}, /* Always on */
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{0xffffffff, {0xffffffff, 0xffffffff}},
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};
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/* All On*/
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/* All On */
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struct msrinit ClockGatingAllOn[] = {
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{GLIU0_GLD_MSR_PM, {.hi=0x00,.lo=0x0FFFFFFFF}},
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{MC_GLD_MSR_PM, {.hi=0x00,.lo=0x0FFFFFFFF}},
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@ -79,7 +78,7 @@ struct msrinit ClockGatingAllOn[] = {
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{0xffffffff, {0xffffffff, 0xffffffff}},
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};
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/* Performance*/
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/* Performance */
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struct msrinit ClockGatingPerformance[] = {
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{VG_GLD_MSR_PM, {.hi=0x00,.lo=0x0000}}, /* lotus #77.163*/
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{GP_GLD_MSR_PM, {.hi=0x00,.lo=0x0001}},
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@ -87,19 +86,18 @@ struct msrinit ClockGatingPerformance[] = {
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{GLCP_GLD_MSR_PM, {.hi=0x00,.lo=0x0015}},
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{0xffffffff, {0xffffffff, 0xffffffff}},
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};
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/* */
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/* SET GeodeLink PRIORITY*/
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/* */
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/* SET GeodeLink PRIORITY */
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struct msrinit GeodeLinkPriorityTable [] = {
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{CPU_GLD_MSR_CONFIG, {.hi=0x00,.lo=0x0220}}, /* CPU Priority.*/
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{DF_GLD_MSR_MASTER_CONF, {.hi=0x00,.lo=0x0000}}, /* DF Priority.*/
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{VG_GLD_MSR_CONFIG, {.hi=0x00,.lo=0x0720}}, /* VG Primary and Secondary Priority.*/
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{GP_GLD_MSR_CONFIG, {.hi=0x00,.lo=0x0010}}, /* Graphics Priority.*/
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{GLPCI_GLD_MSR_CONFIG, {.hi=0x00,.lo=0x0027}}, /* GLPCI Priority + PID*/
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{GLCP_GLD_MSR_CONF, {.hi=0x00,.lo=0x0001}}, /* GLCP Priority + PID*/
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{VIP_GLD_MSR_CONFIG, {.hi=0x00,.lo=0x0622}}, /* VIP PID*/
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{AES_GLD_MSR_CONFIG, {.hi=0x00,.lo=0x0013}}, /* AES PID*/
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{0x0FFFFFFFF, {0x0FFFFFFFF, 0x0FFFFFFFF}}, /* END*/
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{CPU_GLD_MSR_CONFIG, {.hi=0x00,.lo=0x0220}}, /* CPU Priority. */
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{DF_GLD_MSR_MASTER_CONF, {.hi=0x00,.lo=0x0000}}, /* DF Priority. */
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{VG_GLD_MSR_CONFIG, {.hi=0x00,.lo=0x0720}}, /* VG Primary and Secondary Priority. */
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{GP_GLD_MSR_CONFIG, {.hi=0x00,.lo=0x0010}}, /* Graphics Priority. */
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{GLPCI_GLD_MSR_CONFIG, {.hi=0x00,.lo=0x0027}}, /* GLPCI Priority + PID */
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{GLCP_GLD_MSR_CONF, {.hi=0x00,.lo=0x0001}}, /* GLCP Priority + PID */
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{VIP_GLD_MSR_CONFIG, {.hi=0x00,.lo=0x0622}}, /* VIP PID */
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{AES_GLD_MSR_CONFIG, {.hi=0x00,.lo=0x0013}}, /* AES PID */
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{0x0FFFFFFFF, {0x0FFFFFFFF, 0x0FFFFFFFF}}, /* END */
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};
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/* do we have dmi or not? assume NO per AMD */
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@ -111,7 +109,7 @@ writeglmsr(struct gliutable *gl){
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msr.lo = gl->lo;
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msr.hi = gl->hi;
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wrmsr(gl->desc_name, msr); // MSR - see table above
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wrmsr(gl->desc_name, msr); /* MSR - see table above */
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printk(BIOS_DEBUG, "%s: write msr 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo);
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/* they do this, so we do this */
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msr = rdmsr(gl->desc_name);
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@ -131,10 +129,9 @@ ShadowInit(struct gliutable *gl)
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}
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/* NOTE: transcribed from assembly code. There is the usual redundant assembly nonsense in here.
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* CLEAN ME UP
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*/
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/* yes, this duplicates later code, but it seems that is how they want it done.
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*/
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* CLEAN ME UP
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*/
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/* yes, this duplicates later code, but it seems that is how they want it done. */
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static void
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SysmemInit(struct gliutable *gl)
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{
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@ -161,12 +158,12 @@ SysmemInit(struct gliutable *gl)
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sizebytes &= 0xfff00000;
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sizebytes |= 0x100;
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msr.lo = sizebytes;
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wrmsr(gl->desc_name, msr); // MSR - see table above
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wrmsr(gl->desc_name, msr); /* MSR - see table above */
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msr = rdmsr(gl->desc_name);
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printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08lx, val 0x%08x:0x%08x\n", __func__,
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gl->desc_name, msr.hi, msr.lo);
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}
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static void
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DMMGL0Init(struct gliutable *gl) {
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msr_t msr;
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@ -189,11 +186,11 @@ DMMGL0Init(struct gliutable *gl) {
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msr.lo = DMM_OFFSET << 8;
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msr.lo |= ((~(DMM_SIZE*1024)+1)>>12)&0xfffff;
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wrmsr(gl->desc_name, msr); // MSR - See table above
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wrmsr(gl->desc_name, msr); /* MSR - See table above */
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msr = rdmsr(gl->desc_name);
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printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo);
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}
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static void
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DMMGL1Init(struct gliutable *gl) {
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msr_t msr;
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@ -212,10 +209,11 @@ DMMGL1Init(struct gliutable *gl) {
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printk(BIOS_ERR, "%s: warning, using DMM_SIZE even though AMD used SMM_SIZE\n", __func__);
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msr.lo |= ((~(DMM_SIZE*1024)+1)>>12)&0xfffff;
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wrmsr(gl->desc_name, msr); // MSR - See table above
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wrmsr(gl->desc_name, msr); /* MSR - See table above */
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msr = rdmsr(gl->desc_name);
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printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo);
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}
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static void
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SMMGL0Init(struct gliutable *gl) {
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msr_t msr;
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@ -239,10 +237,11 @@ SMMGL0Init(struct gliutable *gl) {
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msr.lo = SMM_OFFSET << 8;
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msr.lo |= ((~(SMM_SIZE*1024)+1)>>12)&0xfffff;
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wrmsr(gl->desc_name, msr); // MSR - See table above
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wrmsr(gl->desc_name, msr); /* MSR - See table above */
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msr = rdmsr(gl->desc_name);
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printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo);
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}
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static void
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SMMGL1Init(struct gliutable *gl) {
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msr_t msr;
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@ -255,7 +254,7 @@ SMMGL1Init(struct gliutable *gl) {
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msr.lo = SMM_OFFSET << 8;
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msr.lo |= ((~(SMM_SIZE*1024)+1)>>12)&0xfffff;
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wrmsr(gl->desc_name, msr); // MSR - See table above
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wrmsr(gl->desc_name, msr); /* MSR - See table above */
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msr = rdmsr(gl->desc_name);
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printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo);
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}
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@ -268,69 +267,58 @@ GLIUInit(struct gliutable *gl){
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default:
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/* For Unknown types: Write then read MSR */
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writeglmsr(gl);
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case SC_SHADOW: /* Check for a Shadow entry*/
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case SC_SHADOW: /* Check for a Shadow entry */
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ShadowInit(gl);
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break;
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case R_SYSMEM: /* check for a SYSMEM entry*/
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case R_SYSMEM: /* check for a SYSMEM entry */
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SysmemInit(gl);
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break;
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case BMO_DMM: /* check for a DMM entry*/
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case BMO_DMM: /* check for a DMM entry */
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DMMGL0Init(gl);
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break;
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case BM_DMM : /* check for a DMM entry*/
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case BM_DMM : /* check for a DMM entry */
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DMMGL1Init(gl);
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break;
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case BMO_SMM : /* check for a SMM entry*/
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case BMO_SMM : /* check for a SMM entry */
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SMMGL0Init(gl);
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break;
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case BM_SMM : /* check for a SMM entry*/
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case BM_SMM : /* check for a SMM entry */
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SMMGL1Init(gl);
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break;
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}
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gl++;
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}
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}
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/* ***************************************************************************/
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/* **/
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/* * GLPCIInit*/
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/* **/
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/* * Set up GLPCI settings for reads/write into memory*/
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/* * R0: 0-640KB,*/
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/* * R1: 1MB - Top of System Memory*/
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/* * R2: SMM Memory*/
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/* * R3: Framebuffer? - not set up yet*/
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/* * R4: ??*/
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/* **/
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/* * Entry:*/
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/* * Exit:*/
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/* * Modified:*/
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/* **/
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/* ***************************************************************************/
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/*
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* Set up GLPCI settings for reads/write into memory.
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*
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* R0: 0-640KB,
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* R1: 1MB - Top of System Memory
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* R2: SMM Memory
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* R3: Framebuffer? - not set up yet
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* R4: ??
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*/
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static void GLPCIInit(void){
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struct gliutable *gl = 0;
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int i;
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msr_t msr;
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int msrnum;
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/* */
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/* R0 - GLPCI settings for Conventional Memory space.*/
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/* */
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msr.hi = (0x09F000 >> 12) << GLPCI_RC_UPPER_TOP_SHIFT /* 640*/;
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msr.lo = 0 /* 0*/;
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/* R0 - GLPCI settings for Conventional Memory space. */
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msr.hi = (0x09F000 >> 12) << GLPCI_RC_UPPER_TOP_SHIFT; /* 640 */
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msr.lo = 0; /* 0 */
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msr.lo |= GLPCI_RC_LOWER_EN_SET+ GLPCI_RC_LOWER_PF_SET + GLPCI_RC_LOWER_WC_SET;
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msrnum = GLPCI_RC0;
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wrmsr(msrnum, msr);
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/* */
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/* R1 - GLPCI settings for SysMem space.*/
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/* */
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/* Get systop from GLIU0 SYSTOP Descriptor*/
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/* R1 - GLPCI settings for SysMem space. */
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/* Get systop from GLIU0 SYSTOP Descriptor */
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for(i = 0; gliu0table[i].desc_name != GL_END; i++) {
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if (gliu0table[i].desc_type == R_SYSMEM) {
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gl = &gliu0table[i];
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@ -345,8 +333,8 @@ static void GLPCIInit(void){
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* translates to a base of 0x00100000 and top of 0xffbf0000
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* base of 1M and top of around 256M
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*/
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/* we have to create a page-aligned (4KB page) address for base and top */
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/* So we need a high page aligned addresss (pah) and low page aligned address (pal)
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/* we have to create a page-aligned (4KB page) address for base and top
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* So we need a high page aligned addresss (pah) and low page aligned address (pal)
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* pah is from msr.hi << 12 | msr.low >> 20. pal is msr.lo << 12
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*/
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printk(BIOS_DEBUG, "GLPCI r1: system msr.lo 0x%08x msr.hi 0x%08x\n", msr.lo, msr.hi);
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@ -363,9 +351,7 @@ static void GLPCIInit(void){
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wrmsr(msrnum, msr);
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}
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/* */
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/* R2 - GLPCI settings for SMM space.*/
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/* */
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/* R2 - GLPCI settings for SMM space. */
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msr.hi = ((SMM_OFFSET+(SMM_SIZE*1024-1)) >> 12) << GLPCI_RC_UPPER_TOP_SHIFT;
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msr.lo = (SMM_OFFSET >> 12) << GLPCI_RC_LOWER_BASE_SHIFT;
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msr.lo |= GLPCI_RC_LOWER_EN_SET | GLPCI_RC_LOWER_PF_SET;
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@ -373,9 +359,9 @@ static void GLPCIInit(void){
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wrmsr(msrnum, msr);
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/* this is done elsewhere already, but it does no harm to do it more than once */
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/* write serialize memory hole to PCI. Need to to unWS when something is shadowed regardless of cachablility.*/
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msr.lo = 0x021212121 /* cache disabled and write serialized*/;
|
||||
msr.hi = 0x021212121 /* cache disabled and write serialized*/;
|
||||
/* write serialize memory hole to PCI. Need to to unWS when something is shadowed regardless of cachablility. */
|
||||
msr.lo = 0x021212121; /* cache disabled and write serialized */
|
||||
msr.hi = 0x021212121; /* cache disabled and write serialized */
|
||||
|
||||
msrnum = CPU_RCONF_A0_BF;
|
||||
wrmsr(msrnum, msr);
|
||||
|
|
@ -386,7 +372,7 @@ static void GLPCIInit(void){
|
|||
msrnum = CPU_RCONF_E0_FF;
|
||||
wrmsr(msrnum, msr);
|
||||
|
||||
/* Set Non-Cacheable Read Only for NorthBound Transactions to Memory. The Enable bit is handled in the Shadow setup.*/
|
||||
/* Set Non-Cacheable Read Only for NorthBound Transactions to Memory. The Enable bit is handled in the Shadow setup. */
|
||||
msrnum = GLPCI_A0_BF;
|
||||
msr.hi = 0x35353535;
|
||||
msr.lo = 0x35353535;
|
||||
|
|
@ -402,29 +388,26 @@ static void GLPCIInit(void){
|
|||
msr.lo = 0x35353535;
|
||||
wrmsr(msrnum, msr);
|
||||
|
||||
/* Set WSREQ*/
|
||||
/* Set WSREQ */
|
||||
msrnum = CPU_DM_CONFIG0;
|
||||
msr = rdmsr(msrnum);
|
||||
msr.hi &= ~ (7 << DM_CONFIG0_UPPER_WSREQ_SHIFT);
|
||||
msr.hi |= 2 << DM_CONFIG0_UPPER_WSREQ_SHIFT ; /* reduce to 1 for safe mode.*/
|
||||
msr.hi |= 2 << DM_CONFIG0_UPPER_WSREQ_SHIFT ; /* reduce to 1 for safe mode. */
|
||||
wrmsr(msrnum, msr);
|
||||
|
||||
/* we are ignoring the 5530 case for now, and perhaps forever. */
|
||||
|
||||
/* */
|
||||
/* 5535 NB Init*/
|
||||
/* */
|
||||
/* 5535 NB Init */
|
||||
msrnum = GLPCI_ARB;
|
||||
msr = rdmsr(msrnum);
|
||||
msr.hi |= GLPCI_ARB_UPPER_PRE0_SET | GLPCI_ARB_UPPER_PRE1_SET;
|
||||
msr.lo |= GLPCI_ARB_LOWER_IIE_SET;
|
||||
wrmsr(msrnum, msr);
|
||||
|
||||
|
||||
msrnum = GLPCI_CTRL;
|
||||
msr = rdmsr(msrnum);
|
||||
|
||||
msr.lo |= GLPCI_CTRL_LOWER_ME_SET | GLPCI_CTRL_LOWER_OWC_SET | GLPCI_CTRL_LOWER_PCD_SET; /* (Out will be disabled in CPUBUG649 for < 2.0 parts .)*/
|
||||
msr.lo |= GLPCI_CTRL_LOWER_ME_SET | GLPCI_CTRL_LOWER_OWC_SET | GLPCI_CTRL_LOWER_PCD_SET; /* (Out will be disabled in CPUBUG649 for < 2.0 parts .) */
|
||||
msr.lo |= GLPCI_CTRL_LOWER_LDE_SET;
|
||||
|
||||
msr.lo &= ~ (0x03 << GLPCI_CTRL_LOWER_IRFC_SHIFT);
|
||||
|
|
@ -449,37 +432,23 @@ static void GLPCIInit(void){
|
|||
msr.hi |= 0x00 << GLPCI_CTRL_UPPER_ILTO_SHIFT;
|
||||
wrmsr(msrnum, msr);
|
||||
|
||||
|
||||
/* Set GLPCI Latency Timer.*/
|
||||
/* Set GLPCI Latency Timer. */
|
||||
msrnum = GLPCI_CTRL;
|
||||
msr = rdmsr(msrnum);
|
||||
msr.hi |= 0x1F << GLPCI_CTRL_UPPER_LAT_SHIFT; /* Change once 1.x is gone.*/
|
||||
msr.hi |= 0x1F << GLPCI_CTRL_UPPER_LAT_SHIFT; /* Change once 1.x is gone. */
|
||||
wrmsr(msrnum, msr);
|
||||
|
||||
/* GLPCI_SPARE*/
|
||||
/* GLPCI_SPARE */
|
||||
msrnum = GLPCI_SPARE;
|
||||
msr = rdmsr(msrnum);
|
||||
msr.lo &= ~ 0x7;
|
||||
msr.lo |= GLPCI_SPARE_LOWER_AILTO_SET | GLPCI_SPARE_LOWER_PPD_SET | GLPCI_SPARE_LOWER_PPC_SET | GLPCI_SPARE_LOWER_MPC_SET | GLPCI_SPARE_LOWER_NSE_SET | GLPCI_SPARE_LOWER_SUPO_SET;
|
||||
wrmsr(msrnum, msr);
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* ***************************************************************************/
|
||||
/* **/
|
||||
/* * ClockGatingInit*/
|
||||
/* **/
|
||||
/* * Enable Clock Gating.*/
|
||||
/* **/
|
||||
/* * Entry:*/
|
||||
/* * Exit:*/
|
||||
/* * Modified:*/
|
||||
/* **/
|
||||
/* ***************************************************************************/
|
||||
static void
|
||||
ClockGatingInit (void){
|
||||
/* Enable Clock Gating. */
|
||||
static void ClockGatingInit (void)
|
||||
{
|
||||
msr_t msr;
|
||||
struct msrinit *gating = ClockGatingDefault;
|
||||
int i;
|
||||
|
|
@ -511,14 +480,13 @@ performance:
|
|||
msr.lo |= gating->msr.lo;
|
||||
printk(BIOS_DEBUG, "%s: MSR 0x%08lx will be set to 0x%08x:0x%08x\n", __func__,
|
||||
gating->msrnum, msr.hi, msr.lo);
|
||||
wrmsr(gating->msrnum, msr); // MSR - See the table above
|
||||
wrmsr(gating->msrnum, msr); /* MSR - See the table above */
|
||||
gating +=1;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
static void
|
||||
GeodeLinkPriority(void){
|
||||
static void GeodeLinkPriority(void)
|
||||
{
|
||||
msr_t msr;
|
||||
struct msrinit *prio = GeodeLinkPriorityTable;
|
||||
int i;
|
||||
|
|
@ -531,17 +499,16 @@ GeodeLinkPriority(void){
|
|||
msr.lo |= prio->msr.lo;
|
||||
printk(BIOS_DEBUG, "%s: MSR 0x%08lx will be set to 0x%08x:0x%08x\n", __func__,
|
||||
prio->msrnum, msr.hi, msr.lo);
|
||||
wrmsr(prio->msrnum, msr); // MSR - See the table above
|
||||
wrmsr(prio->msrnum, msr); /* MSR - See the table above */
|
||||
prio +=1;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* Get the GLIU0 shadow register settings
|
||||
* If the setShadow function is used then all shadow descriptors
|
||||
* will stay sync'ed.
|
||||
* Get the GLIU0 shadow register settings.
|
||||
*
|
||||
* If the setShadow function is used then all shadow descriptors
|
||||
* will stay sync'ed.
|
||||
*/
|
||||
static uint64_t getShadow(void)
|
||||
{
|
||||
|
|
@ -550,83 +517,81 @@ static uint64_t getShadow(void)
|
|||
return ( ( (uint64_t) msr.hi ) << 32 ) | msr.lo;
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Set the cache RConf registers for the memory hole.
|
||||
* Keeps all cache shadow descriptors sync'ed.
|
||||
* This is part of the PCI lockup solution
|
||||
* Entry: EDX:EAX is the shadow settings
|
||||
* Set the cache RConf registers for the memory hole.
|
||||
*
|
||||
* Keeps all cache shadow descriptors sync'ed.
|
||||
* This is part of the PCI lockup solution.
|
||||
*
|
||||
* Entry: EDX:EAX is the shadow settings.
|
||||
*/
|
||||
static void setShadowRCONF(uint32_t shadowHi, uint32_t shadowLo)
|
||||
{
|
||||
// ok this is whacky bit translation time.
|
||||
/* ok this is whacky bit translation time. */
|
||||
int bit;
|
||||
uint8_t shadowByte;
|
||||
msr_t msr;
|
||||
shadowByte = (uint8_t) (shadowLo >> 16);
|
||||
|
||||
// load up D000 settings in edx.
|
||||
/* load up D000 settings in edx. */
|
||||
for (bit = 8; (bit > 4); bit--) {
|
||||
msr.hi <<= 8;
|
||||
msr.hi |= 1; // cache disable PCI/Shadow memory
|
||||
msr.hi |= 1; /* cache disable PCI/Shadow memory */
|
||||
if (shadowByte && (1 << bit))
|
||||
msr.hi |= 0x20; // write serialize PCI memory
|
||||
msr.hi |= 0x20; /* write serialize PCI memory */
|
||||
}
|
||||
|
||||
// load up C000 settings in eax.
|
||||
/* load up C000 settings in eax. */
|
||||
for ( ; bit; bit--) {
|
||||
msr.lo <<= 8;
|
||||
msr.lo |= 1; // cache disable PCI/Shadow memory
|
||||
msr.lo |= 1; /* cache disable PCI/Shadow memory */
|
||||
if (shadowByte && (1 << bit))
|
||||
msr.lo |= 0x20; // write serialize PCI memory
|
||||
msr.lo |= 0x20; /* write serialize PCI memory */
|
||||
}
|
||||
|
||||
wrmsr(CPU_RCONF_C0_DF, msr);
|
||||
|
||||
shadowByte = (uint8_t) (shadowLo >> 24);
|
||||
|
||||
// load up F000 settings in edx.
|
||||
/* load up F000 settings in edx. */
|
||||
for (bit = 8; (bit > 4); bit--) {
|
||||
msr.hi <<= 8;
|
||||
msr.hi |= 1; // cache disable PCI/Shadow memory
|
||||
msr.hi |= 1; /* cache disable PCI/Shadow memory */
|
||||
if (shadowByte && (1 << bit))
|
||||
msr.hi |= 0x20; // write serialize PCI memory
|
||||
msr.hi |= 0x20; /* write serialize PCI memory */
|
||||
}
|
||||
|
||||
// load up E000 settings in eax.
|
||||
/* load up E000 settings in eax. */
|
||||
for ( ; bit; bit--) {
|
||||
msr.lo <<= 8;
|
||||
msr.lo |= 1; // cache disable PCI/Shadow memory
|
||||
msr.lo |= 1; /* cache disable PCI/Shadow memory */
|
||||
if (shadowByte && (1 << bit))
|
||||
msr.lo |= 0x20; // write serialize PCI memory
|
||||
msr.lo |= 0x20; /* write serialize PCI memory */
|
||||
}
|
||||
|
||||
wrmsr(CPU_RCONF_E0_FF, msr);
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Set the GLPCI registers for the memory hole.
|
||||
* Keeps all cache shadow descriptors sync'ed.
|
||||
* Entry: EDX:EAX is the shadow settings
|
||||
* Set the GLPCI registers for the memory hole.
|
||||
* Keeps all cache shadow descriptors sync'ed.
|
||||
* Entry: EDX:EAX is the shadow settings
|
||||
*/
|
||||
static void setShadowGLPCI(uint32_t shadowHi, uint32_t shadowLo)
|
||||
{
|
||||
msr_t msr;
|
||||
|
||||
// Set the Enable Register.
|
||||
|
||||
/* Set the Enable Register. */
|
||||
msr = rdmsr(GLPCI_REN);
|
||||
msr.lo &= 0xFFFF00FF;
|
||||
msr.lo |= ( (shadowLo & 0xFFFF0000) >> 8);
|
||||
wrmsr(GLPCI_REN, msr);
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Set the GLIU SC register settings. Scans descriptor tables for SC_SHADOW.
|
||||
* Keeps all shadow descriptors sync'ed.
|
||||
* Entry: EDX:EAX is the shadow settings
|
||||
* Set the GLIU SC register settings. Scans descriptor tables for SC_SHADOW.
|
||||
* Keeps all shadow descriptors sync'ed.
|
||||
* Entry: EDX:EAX is the shadow settings
|
||||
*/
|
||||
static void setShadow(uint64_t shadowSettings)
|
||||
{
|
||||
|
|
@ -647,50 +612,34 @@ static void setShadow(uint64_t shadowSettings)
|
|||
|
||||
msr = rdmsr(pTable->desc_name);
|
||||
msr.lo = (uint32_t) shadowSettings;
|
||||
msr.hi &= 0xFFFF0000; // maintain PDID in upper EDX
|
||||
msr.hi &= 0xFFFF0000; /* maintain PDID in upper EDX */
|
||||
msr.hi |= ((uint32_t) (shadowSettings >> 32)) & 0x0000FFFF;
|
||||
wrmsr(pTable->desc_name, msr); // MSR - See the table above
|
||||
wrmsr(pTable->desc_name, msr); /* MSR - See the table above */
|
||||
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**************************************************************************
|
||||
*
|
||||
* shadowRom
|
||||
*
|
||||
* Set up a stack for ease of further testing
|
||||
*
|
||||
* Entry:
|
||||
* Exit:
|
||||
* Destroys:
|
||||
*
|
||||
**************************************************************************/
|
||||
static void
|
||||
shadowRom(void)
|
||||
/* Set up a stack for ease of further testing. */
|
||||
static void shadowRom(void)
|
||||
{
|
||||
uint64_t shadowSettings = getShadow();
|
||||
shadowSettings &= (uint64_t) 0xFFFF00000000FFFFULL; // Disable read & writes
|
||||
shadowSettings |= (uint64_t) 0x0000FFFFFFFF0000ULL; // Enable reads for C0000-FFFFF
|
||||
shadowSettings &= (uint64_t) 0xFFFF00000000FFFFULL; /* Disable read & writes */
|
||||
shadowSettings |= (uint64_t) 0x0000FFFFFFFF0000ULL; /* Enable reads for C0000-FFFFF */
|
||||
setShadow(shadowSettings);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/***************************************************************************
|
||||
/*
|
||||
* Set up RCONF_DEFAULT and any other RCONF registers needed.
|
||||
*
|
||||
* RCONFInit
|
||||
* Set up RCONF_DEFAULT and any other RCONF registers needed
|
||||
*
|
||||
* DEVRC_RCONF_DEFAULT:
|
||||
* ROMRC(63:56) = 04h ; write protect ROMBASE
|
||||
* ROMBASE(36:55) = 0FFFC0h ; Top of PCI/bottom of rom chipselect area
|
||||
* DEVRC(35:28) = 39h ; cache disabled in PCI memory + WS bit on + Write Combine + write burst.
|
||||
* SYSTOP(27:8) = top of system memory
|
||||
* SYSRC(7:0) = 00h ; writeback, can set to 08h to make writethrough
|
||||
*
|
||||
***************************************************************************/
|
||||
* DEVRC_RCONF_DEFAULT:
|
||||
* ROMRC(63:56) = 04h ; write protect ROMBASE
|
||||
* ROMBASE(36:55) = 0FFFC0h ; Top of PCI/bottom of rom chipselect area
|
||||
* DEVRC(35:28) = 39h ; cache disabled in PCI memory + WS bit on + Write Combine + write burst.
|
||||
* SYSTOP(27:8) = top of system memory
|
||||
* SYSRC(7:0) = 00h ; writeback, can set to 08h to make writethrough
|
||||
*/
|
||||
#define SYSMEM_RCONF_WRITETHROUGH 8
|
||||
#define DEVRC_RCONF_DEFAULT 0x21
|
||||
#define ROMBASE_RCONF_DEFAULT 0xFFFC0000
|
||||
|
|
@ -712,11 +661,11 @@ RCONFInit(void)
|
|||
}
|
||||
}
|
||||
if (gl == 0) {
|
||||
post_code(0xCE); /* POST_RCONFInitError */
|
||||
post_code(0xCE); /* POST_RCONFInitError */
|
||||
while (1);
|
||||
}
|
||||
|
||||
// sysdescfound:
|
||||
/* sysdescfound: */
|
||||
/* found the descriptor... get its contents */
|
||||
msr = rdmsr(gl->desc_name);
|
||||
|
||||
|
|
@ -725,26 +674,26 @@ RCONFInit(void)
|
|||
*/
|
||||
msr.lo = (msr.lo & 0xFFFFFF00) | (msr.hi & 0xFF);
|
||||
msr.lo = ((msr.lo << 12) | (msr.lo >> 20)) & 0x000FFFFF;
|
||||
msr.lo <<= RCONF_DEFAULT_LOWER_SYSTOP_SHIFT; // 8
|
||||
msr.lo <<= RCONF_DEFAULT_LOWER_SYSTOP_SHIFT; /* 8 */
|
||||
|
||||
// Set Default SYSMEM region properties
|
||||
msr.lo &= ~SYSMEM_RCONF_WRITETHROUGH; // 8 (or ~8)
|
||||
/* Set Default SYSMEM region properties */
|
||||
msr.lo &= ~SYSMEM_RCONF_WRITETHROUGH; /* 8 (or ~8) */
|
||||
|
||||
// Set PCI space cache properties
|
||||
msr.hi = (DEVRC_RCONF_DEFAULT >> 4); // only need the bottom bits and lets clean the rest of edx
|
||||
/* Set PCI space cache properties */
|
||||
msr.hi = (DEVRC_RCONF_DEFAULT >> 4); /* only need the bottom bits and lets clean the rest of edx */
|
||||
msr.lo |= (DEVRC_RCONF_DEFAULT << 28);
|
||||
|
||||
// Set the ROMBASE. This is usually FFFC0000h
|
||||
/* Set the ROMBASE. This is usually FFFC0000h */
|
||||
msr.hi |= (ROMBASE_RCONF_DEFAULT >> 12) << RCONF_DEFAULT_UPPER_ROMBASE_SHIFT;
|
||||
|
||||
// Set ROMBASE cache properties.
|
||||
/* Set ROMBASE cache properties. */
|
||||
msr.hi |= ((ROMRC_RCONF_DEFAULT >> 8) | (ROMRC_RCONF_DEFAULT << 24));
|
||||
|
||||
// now program RCONF_DEFAULT
|
||||
/* now program RCONF_DEFAULT */
|
||||
wrmsr(CPU_RCONF_DEFAULT, msr);
|
||||
|
||||
// RCONF_BYPASS: Cache tablewalk properties and SMM/DMM header access properties.
|
||||
// Set to match system memory cache properties.
|
||||
/* RCONF_BYPASS: Cache tablewalk properties and SMM/DMM header access properties. */
|
||||
/* Set to match system memory cache properties. */
|
||||
msr = rdmsr(CPU_RCONF_DEFAULT);
|
||||
SysMemCacheProp = (uint8_t) (msr.lo & 0xFF);
|
||||
msr = rdmsr(CPU_RCONF_BYPASS);
|
||||
|
|
@ -752,21 +701,8 @@ RCONFInit(void)
|
|||
wrmsr(CPU_RCONF_BYPASS, msr);
|
||||
}
|
||||
|
||||
|
||||
/* ***************************************************************************/
|
||||
/* **/
|
||||
/* * northBridgeInit*/
|
||||
/* **/
|
||||
/* * Core Logic initialization: Host bridge*/
|
||||
/* **/
|
||||
/* * Entry:*/
|
||||
/* * Exit:*/
|
||||
/* * Modified:*/
|
||||
/* **/
|
||||
/* ***************************************************************************/
|
||||
|
||||
void
|
||||
northbridgeinit(void)
|
||||
/* Core Logic initialization: Host bridge. */
|
||||
void northbridgeinit(void)
|
||||
{
|
||||
msr_t msr;
|
||||
int i;
|
||||
|
|
@ -779,22 +715,23 @@ northbridgeinit(void)
|
|||
|
||||
shadowRom();
|
||||
|
||||
// GeodeROM ensures that the BIOS waits the required 1 second before
|
||||
// allowing anything to access PCI
|
||||
/* GeodeROM ensures that the BIOS waits the required 1 second before */
|
||||
/* allowing anything to access PCI */
|
||||
// PCIDelay();
|
||||
|
||||
RCONFInit();
|
||||
|
||||
// The cacheInit function in GeodeROM tests cache and, among other things,
|
||||
// makes sure all INVD instructions are treated as WBINVD. We do this
|
||||
// because we've found some programs which require this behavior.
|
||||
// That subset of cacheInit() is implemented here:
|
||||
/* The cacheInit function in GeodeROM tests cache and, among other things,
|
||||
* makes sure all INVD instructions are treated as WBINVD. We do this
|
||||
* because we've found some programs which require this behavior.
|
||||
* That subset of cacheInit() is implemented here:
|
||||
*/
|
||||
msr = rdmsr(CPU_DM_CONFIG0);
|
||||
msr.lo |= DM_CONFIG0_LOWER_WBINVD_SET;
|
||||
wrmsr(CPU_DM_CONFIG0, msr);
|
||||
|
||||
/* Now that the descriptor to memory is set up.*/
|
||||
/* The memory controller needs one read to synch its lines before it can be used.*/
|
||||
/* Now that the descriptor to memory is set up. */
|
||||
/* The memory controller needs one read to synch its lines before it can be used. */
|
||||
i = *(int *) 0;
|
||||
|
||||
GLPCIInit();
|
||||
|
|
|
|||
|
|
@ -80,12 +80,13 @@ static void auto_size_dimm(unsigned int dimm)
|
|||
dimm_setting |= (spd_byte >> 2) << CF07_UPPER_D0_CB_SHIFT;
|
||||
banner("SPDNUMROWS");
|
||||
|
||||
/*; Field: DIMM size
|
||||
*; EEPROM byte usage: (3) Number of Row Addresses
|
||||
*; (4) Number of Column Addresses
|
||||
*; (5) Number of DIMM Banks
|
||||
*; (31) Module Bank Density
|
||||
*; Size = Module Density * Module Banks
|
||||
/* Field: DIMM size
|
||||
* EEPROM byte usage:
|
||||
* (3) Number of Row Addresses
|
||||
* (4) Number of Column Addresses
|
||||
* (5) Number of DIMM Banks
|
||||
* (31) Module Bank Density
|
||||
* Size = Module Density * Module Banks
|
||||
*/
|
||||
if ((spd_read_byte(dimm, SPD_NUM_ROWS) & 0xF0)
|
||||
|| (spd_read_byte(dimm, SPD_NUM_COLUMNS) & 0xF0)) {
|
||||
|
|
@ -100,7 +101,7 @@ static void auto_size_dimm(unsigned int dimm)
|
|||
dimm_size |= (dimm_size << 8); /* align so 1GB(bit0) is bit 8, this is a little weird to get gcc to not optimize this out */
|
||||
dimm_size &= 0x01FC; /* and off 2GB DIMM size : not supported and the 1GB size we just moved up to bit 8 as well as all the extra on top */
|
||||
|
||||
/* Module Density * Module Banks */
|
||||
/* Module Density * Module Banks */
|
||||
dimm_size <<= (dimm_setting >> CF07_UPPER_D0_MB_SHIFT) & 1; /* shift to multiply by # DIMM banks */
|
||||
banner("BEFORT CTZ");
|
||||
dimm_size = __builtin_ctz(dimm_size);
|
||||
|
|
@ -113,27 +114,32 @@ static void auto_size_dimm(unsigned int dimm)
|
|||
dimm_setting |= dimm_size << CF07_UPPER_D0_SZ_SHIFT;
|
||||
banner("PAGESIZE");
|
||||
|
||||
/*; Field: PAGE size
|
||||
*; EEPROM byte usage: (4) Number of Column Addresses
|
||||
*; PageSize = 2^# Column Addresses * Data width in bytes (should be 8bytes for a normal DIMM)
|
||||
*
|
||||
*; But this really works by magic.
|
||||
*; If ma[11:0] is the memory address pins, and pa[13:0] is the physical column address
|
||||
*; that MC generates, here is how the MC assigns the pa onto the ma pins:
|
||||
*
|
||||
*;ma 11 10 09 08 07 06 05 04 03 02 01 00
|
||||
*;--------------------------------------------------------------------------------------------------------------------------------------
|
||||
*;pa 09 08 07 06 05 04 03 (7 col addr bits = 1K page size)
|
||||
*;pa 10 09 08 07 06 05 04 03 (8 col addr bits = 2K page size)
|
||||
*;pa 11 10 09 08 07 06 05 04 03 (9 col addr bits = 4K page size)
|
||||
*;pa 12 11 10 09 08 07 06 05 04 03 (10 col addr bits = 8K page size)
|
||||
*;pa 13 AP 12 11 10 09 08 07 06 05 04 03 (11 col addr bits = 16K page size)
|
||||
*; *AP=autoprecharge bit
|
||||
*
|
||||
*; Remember that pa[2:0] are zeroed out since it's a 64-bit data bus (8 bytes),
|
||||
*; so lower 3 address bits are dont_cares.So from the table above,
|
||||
*; it's easier to see what the old code is doing: if for example,#col_addr_bits=7(06h),
|
||||
*; it adds 3 to get 10, then does 2^10=1K. Get it?*/
|
||||
/*
|
||||
* Field: PAGE size
|
||||
* EEPROM byte usage: (4) Number of Column Addresses
|
||||
* PageSize = 2^# Column Addresses * Data width in bytes
|
||||
* (should be 8bytes for a normal DIMM)
|
||||
*
|
||||
* But this really works by magic.
|
||||
* If ma[11:0] is the memory address pins, and pa[13:0] is the physical column
|
||||
* address that MC generates, here is how the MC assigns the pa onto the
|
||||
* ma pins:
|
||||
*
|
||||
* ma 11 10 09 08 07 06 05 04 03 02 01 00
|
||||
* ---------------------------------------
|
||||
* pa 09 08 07 06 05 04 03 (7 col addr bits = 1K page size)
|
||||
* pa 10 09 08 07 06 05 04 03 (8 col addr bits = 2K page size)
|
||||
* pa 11 10 09 08 07 06 05 04 03 (9 col addr bits = 4K page size)
|
||||
* pa 12 11 10 09 08 07 06 05 04 03 (10 col addr bits = 8K page size)
|
||||
* pa 13 AP 12 11 10 09 08 07 06 05 04 03 (11 col addr bits = 16K page size)
|
||||
*
|
||||
* (AP = autoprecharge bit)
|
||||
*
|
||||
* Remember that pa[2:0] are zeroed out since it's a 64-bit data bus (8 bytes),
|
||||
* so lower 3 address bits are dont_cares. So from the table above,
|
||||
* it's easier to see what the old code is doing: if for example,
|
||||
* #col_addr_bits=7(06h), it adds 3 to get 10, then does 2^10=1K.
|
||||
*/
|
||||
|
||||
spd_byte = NumColAddr[spd_read_byte(dimm, SPD_NUM_COLUMNS) & 0xF];
|
||||
banner("MAXCOLADDR");
|
||||
|
|
@ -269,26 +275,25 @@ static u8 getcasmap(u32 dimm, u16 glspeed)
|
|||
|
||||
static void setCAS(void)
|
||||
{
|
||||
/*;*****************************************************************************
|
||||
;*
|
||||
;* setCAS
|
||||
;* EEPROM byte usage: (18) SDRAM device attributes - CAS latency
|
||||
;* EEPROM byte usage: (23) SDRAM Minimum Clock Cycle Time @ CLX -.5
|
||||
;* EEPROM byte usage: (25) SDRAM Minimum Clock Cycle Time @ CLX -1
|
||||
;*
|
||||
;* The CAS setting is based on the information provided in each DIMMs SPD.
|
||||
;* The speed at which a DIMM can run is described relative to the slowest
|
||||
;* CAS the DIMM supports. Each speed for the relative CAS settings is
|
||||
;* checked that it is within the GeodeLink speed. If it isn't within the GeodeLink
|
||||
;* speed, the CAS setting is removed from the list of good settings for
|
||||
;* the DIMM. This is done for both DIMMs and the lists are compared to
|
||||
;* find the lowest common CAS latency setting. If there are no CAS settings
|
||||
;* in common we out a ERROR_DIFF_DIMMS (78h) to port 80h and halt.
|
||||
;*
|
||||
;* Entry:
|
||||
;* Exit: Set fastest CAS Latency based on GeodeLink speed and SPD information.
|
||||
;* Destroys: We really use everything !
|
||||
;*****************************************************************************/
|
||||
/*
|
||||
* setCAS
|
||||
* EEPROM byte usage: (18) SDRAM device attributes - CAS latency
|
||||
* EEPROM byte usage: (23) SDRAM Minimum Clock Cycle Time @ CLX -.5
|
||||
* EEPROM byte usage: (25) SDRAM Minimum Clock Cycle Time @ CLX -1
|
||||
*
|
||||
* The CAS setting is based on the information provided in each DIMMs SPD.
|
||||
* The speed at which a DIMM can run is described relative to the slowest
|
||||
* CAS the DIMM supports. Each speed for the relative CAS settings is
|
||||
* checked that it is within the GeodeLink speed. If it isn't within the GeodeLink
|
||||
* speed, the CAS setting is removed from the list of good settings for
|
||||
* the DIMM. This is done for both DIMMs and the lists are compared to
|
||||
* find the lowest common CAS latency setting. If there are no CAS settings
|
||||
* in common we out a ERROR_DIFF_DIMMS (78h) to port 80h and halt.
|
||||
*
|
||||
* Entry:
|
||||
* Exit: Set fastest CAS Latency based on GeodeLink speed and SPD information.
|
||||
* Destroys: We really use everything !
|
||||
*/
|
||||
uint16_t glspeed;
|
||||
uint8_t spd_byte, casmap0, casmap1;
|
||||
msr_t msr;
|
||||
|
|
@ -298,7 +303,7 @@ static void setCAS(void)
|
|||
casmap0 = getcasmap(DIMM0, glspeed);
|
||||
casmap1 = getcasmap(DIMM1, glspeed);
|
||||
|
||||
/********************* CAS_LAT MAP COMPARE ***************************/
|
||||
/* CAS_LAT MAP COMPARE */
|
||||
if (casmap0 == 0) {
|
||||
spd_byte = CASDDR[__builtin_ctz(casmap1)];
|
||||
} else if (casmap1 == 0) {
|
||||
|
|
@ -468,7 +473,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl)
|
|||
uint8_t spd_byte;
|
||||
|
||||
banner("sdram_set_spd_register");
|
||||
post_code(POST_MEM_SETUP); // post_70h
|
||||
post_code(POST_MEM_SETUP); /* post_70h */
|
||||
|
||||
spd_byte = spd_read_byte(DIMM0, SPD_MODULE_ATTRIBUTES);
|
||||
banner("Check DIMM 0");
|
||||
|
|
@ -486,23 +491,23 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl)
|
|||
hcf();
|
||||
}
|
||||
|
||||
post_code(POST_MEM_SETUP2); // post_72h
|
||||
post_code(POST_MEM_SETUP2); /* post_72h */
|
||||
banner("Check DDR MAX");
|
||||
|
||||
/* Check that the memory is not overclocked. */
|
||||
checkDDRMax();
|
||||
|
||||
/* Size the DIMMS */
|
||||
post_code(POST_MEM_SETUP3); // post_73h
|
||||
post_code(POST_MEM_SETUP3); /* post_73h */
|
||||
banner("AUTOSIZE DIMM 0");
|
||||
auto_size_dimm(DIMM0);
|
||||
post_code(POST_MEM_SETUP4); // post_74h
|
||||
post_code(POST_MEM_SETUP4); /* post_74h */
|
||||
banner("AUTOSIZE DIMM 1");
|
||||
auto_size_dimm(DIMM1);
|
||||
|
||||
/* Set CAS latency */
|
||||
banner("set cas latency");
|
||||
post_code(POST_MEM_SETUP5); // post_75h
|
||||
post_code(POST_MEM_SETUP5); /* post_75h */
|
||||
setCAS();
|
||||
|
||||
/* Set all the other latencies here (tRAS, tRP....) */
|
||||
|
|
@ -563,7 +568,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
|
|||
//print_debug("sdram_enable step 6\n");
|
||||
|
||||
/* 7. Reset DLL, Bit 27 is undocumented in GX datasheet,
|
||||
* it is documented in LX datasheet */
|
||||
* it is documented in LX datasheet */
|
||||
/* load Mode Register by set and clear PROG_DRAM */
|
||||
msr = rdmsr(MC_CF07_DATA);
|
||||
msr.lo |= ((0x01 << 27) | 0x01);
|
||||
|
|
|
|||
Loading…
Reference in New Issue