AGESA f15 vendorcode: Remove unused sources
Change-Id: Id1ed36e7e76d25cdc9e86254b108deaca0f8b423 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21265 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This commit is contained in:
Kyösti Mälkki
parent
74ecfef2a5
commit
5bf3457bc4
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@ -1,439 +0,0 @@
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/* $NoKeywords:$ */
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/**
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* @file
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*
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* AMD Family_10 Rev C HT PCI tables with values as defined in BKDG
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*
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* @xrefitem bom "File Content Label" "Release Content"
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* @e project: AGESA
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* @e sub-project: CPU/FAMILY/0x10
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* @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $
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*
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*/
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/*
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******************************************************************************
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*
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* Copyright (C) 2012 Advanced Micro Devices, Inc.
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* All rights reserved.
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||||
*
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||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
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||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
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* its contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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||||
*
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||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************
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*/
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/*----------------------------------------------------------------------------------------
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* M O D U L E S U S E D
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*----------------------------------------------------------------------------------------
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*/
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#include "AGESA.h"
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#include "cpuRegisters.h"
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#include "Table.h"
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#include "Filecode.h"
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CODE_GROUP (G1_PEICC)
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RDATA_GROUP (G2_PEI)
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#define FILECODE PROC_CPU_FAMILY_0X10_REVC_F10REVCHTPHYTABLES_FILECODE
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/*----------------------------------------------------------------------------------------
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* D E F I N I T I O N S A N D M A C R O S
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*----------------------------------------------------------------------------------------
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*/
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/*----------------------------------------------------------------------------------------
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* T Y P E D E F S A N D S T R U C T U R E S
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*----------------------------------------------------------------------------------------
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*/
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/*----------------------------------------------------------------------------------------
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* P R O T O T Y P E S O F L O C A L F U N C T I O N S
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*----------------------------------------------------------------------------------------
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*/
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/*----------------------------------------------------------------------------------------
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* E X P O R T E D F U N C T I O N S
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*----------------------------------------------------------------------------------------
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*/
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// HT Phy T a b l e s
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// -------------------------
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STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F10RevCHtPhyRegisters[] =
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{
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// 0x60:0x68
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{
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HtPhyRangeRegister,
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{
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AMD_FAMILY_10, // CpuFamily
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AMD_F10_GT_C0 // CpuRevision
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},
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{AMD_PF_ALL}, // platformFeatures
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{{
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HTPHY_LINKTYPE_SL0_ALL, //
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0x60, 0x68, // Address range
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0x00000040, // regData
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0x00000040, // regMask
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}}
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},
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// 0x70:0x78
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{
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HtPhyRangeRegister,
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{
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AMD_FAMILY_10, // CpuFamily
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AMD_F10_GT_C0 // CpuRevision
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},
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{AMD_PF_ALL}, // platformFeatures
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{{
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HTPHY_LINKTYPE_SL1_ALL, //
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0x70, 0x78, // Address range
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0x00000040, // regData
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0x00000040, // regMask
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}}
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},
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// Erratum 354
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// 0x40:48
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{
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HtPhyRangeRegister,
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{
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AMD_FAMILY_10, // CpuFamily
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(AMD_F10_C2 | AMD_F10_C3) // CpuRevision
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},
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{AMD_PF_ALL}, // platformFeatures
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{{
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HTPHY_LINKTYPE_SL0_HT3, //
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0x40, 0x48, // Address
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0x00000040, // regData
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0x00000040, // regMask
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}}
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},
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// 0x50:0x58
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{
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HtPhyRangeRegister,
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{
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AMD_FAMILY_10, // CpuFamily
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(AMD_F10_C2 | AMD_F10_C3) // CpuRevision
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},
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{AMD_PF_ALL}, // platformFeatures
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{{
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HTPHY_LINKTYPE_SL1_HT3, //
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0x50, 0x58, // Address
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0x00000040, // regData
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0x00000040, // regMask
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}}
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},
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// 0xC0
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{
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HtPhyRegister,
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{
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AMD_FAMILY_10, // CpuFamily
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AMD_F10_Cx // CpuRevision
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},
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{AMD_PF_ALL}, // platformFeatures
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{{
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HTPHY_LINKTYPE_SL0_ALL, //
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0xC0, // Address
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0x40040000, // regData
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0xe01F0000, // regMask
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}}
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},
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// 0xD0
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{
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HtPhyRegister,
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{
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AMD_FAMILY_10, // CpuFamily
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AMD_F10_Cx // CpuRevision
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},
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{AMD_PF_ALL}, // platformFeatures
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{{
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HTPHY_LINKTYPE_SL1_ALL, //
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0xD0, // Address
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0x40040000, // regData
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0xe01F0000, // regMask
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}}
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},
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// 0xCF
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// FIFO_PTR_OPT_VALUE
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{
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HtPhyProfileRegister,
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{
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AMD_FAMILY_10, // CpuFamily
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AMD_F10_C3 // CpuRevision
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},
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{AMD_PF_ALL}, // platformFeatures
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{{
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PERFORMANCE_NB_PSTATES_ENABLE,
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HTPHY_LINKTYPE_SL0_HT3, //
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0xCF, // Address
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0x0000004A, // regData
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0x000000FF, // regMask
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}}
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},
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// 0xDF
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// FIFO_PTR_OPT_VALUE
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{
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HtPhyProfileRegister,
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{
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AMD_FAMILY_10, // CpuFamily
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AMD_F10_C3 // CpuRevision
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},
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{AMD_PF_ALL}, // platformFeatures
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{{
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PERFORMANCE_NB_PSTATES_ENABLE,
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HTPHY_LINKTYPE_SL1_HT3, //
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0xDF, // Address
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0x0000004A, // regData
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0x000000FF, // regMask
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}}
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},
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// 0x520A
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{
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HtPhyRegister,
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{
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AMD_FAMILY_10, // CpuFamily
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AMD_F10_Cx // CpuRevision
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},
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{AMD_PF_ALL}, // platformFeatures
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{{
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HTPHY_LINKTYPE_SL0_ALL, //
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0x520A, // Address
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0x00004000, // regData
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0x00006000, // regMask
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}}
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},
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// 0x530A
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{
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HtPhyRegister,
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{
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AMD_FAMILY_10, // CpuFamily
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AMD_F10_Cx // CpuRevision
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},
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{AMD_PF_ALL}, // platformFeatures
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{{
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HTPHY_LINKTYPE_SL1_ALL, //
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0x530A, // Address
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0x00004000, // regData
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0x00006000, // regMask
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}}
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},
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//
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// Deemphasis Settings
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//
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// For C3, also set [7]TxLs23ClkGateEn.
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//deemphasis level DL1[20:16], DL2[12:8], DP1[4:0] PostCur1En[31] PostCur2En[30] PreCur1En[29] MapPostCur2En[6]
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// No deemphasis 00h 00h 00h 0 0 0 0
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// -3dB postcursor 12h 00h 00h 1 0 0 0
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// -6dB postcursor 1Fh 00h 00h 1 0 0 0
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// -8dB postcursor 1Fh 06h 00h 1 1 0 1
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// -11dB postcursor 1Fh 0Dh 00h 1 1 0 1
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// -11dB postcursor with
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// -8dB precursor 1Fh 06h 07h 1 1 1 1
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{
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DeemphasisRegister,
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{
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AMD_FAMILY_10, // CpuFamily
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AMD_F10_C3 // CpuRevision
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},
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{AMD_PF_ALL}, // platformFeatures
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{{
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DEEMPHASIS_LEVEL_NONE,
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HTPHY_LINKTYPE_SL0_HT3, //
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0xC5, // Address
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0x00000080, // regData
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0xE01F1FDF, // regMask
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}}
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},
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{
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DeemphasisRegister,
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{
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AMD_FAMILY_10, // CpuFamily
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AMD_F10_C3 // CpuRevision
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},
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{AMD_PF_ALL}, // platformFeatures
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{{
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DEEMPHASIS_LEVEL_NONE,
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HTPHY_LINKTYPE_SL1_HT3, //
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0xD5, // Address
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0x00000080, // regData
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0xE01F1FDF, // regMask
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}}
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},
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{
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DeemphasisRegister,
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{
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AMD_FAMILY_10, // CpuFamily
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AMD_F10_C3 // CpuRevision
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},
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{AMD_PF_ALL}, // platformFeatures
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{{
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DEEMPHASIS_LEVEL__3,
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HTPHY_LINKTYPE_SL0_HT3, //
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0xC5, // Address
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0x80120080, // regData
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0xE01F1FDF, // regMask
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}}
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},
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{
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DeemphasisRegister,
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{
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AMD_FAMILY_10, // CpuFamily
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AMD_F10_C3 // CpuRevision
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},
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{AMD_PF_ALL}, // platformFeatures
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{{
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DEEMPHASIS_LEVEL__3,
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HTPHY_LINKTYPE_SL1_HT3, //
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0xD5, // Address
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0x80120080, // regData
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0xE01F1FDF, // regMask
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}}
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},
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{
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DeemphasisRegister,
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{
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AMD_FAMILY_10, // CpuFamily
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AMD_F10_C3 // CpuRevision
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},
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{AMD_PF_ALL}, // platformFeatures
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{{
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DEEMPHASIS_LEVEL__6,
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HTPHY_LINKTYPE_SL0_HT3, //
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0xC5, // Address
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0x801F0080, // regData
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0xE01F1FDF, // regMask
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}}
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},
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{
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DeemphasisRegister,
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{
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AMD_FAMILY_10, // CpuFamily
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AMD_F10_C3 // CpuRevision
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},
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{AMD_PF_ALL}, // platformFeatures
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{{
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DEEMPHASIS_LEVEL__6,
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HTPHY_LINKTYPE_SL1_HT3, //
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0xD5, // Address
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0x801F0080, // regData
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0xE01F1FDF, // regMask
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}}
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},
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{
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DeemphasisRegister,
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{
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AMD_FAMILY_10, // CpuFamily
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AMD_F10_C3 // CpuRevision
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},
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{AMD_PF_ALL}, // platformFeatures
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{{
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DEEMPHASIS_LEVEL__8,
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HTPHY_LINKTYPE_SL0_HT3, //
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0xC5, // Address
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0xC01F06C0, // regData
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0xE01F1FDF, // regMask
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}}
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},
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{
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DeemphasisRegister,
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{
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AMD_FAMILY_10, // CpuFamily
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AMD_F10_C3 // CpuRevision
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},
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{AMD_PF_ALL}, // platformFeatures
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{{
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DEEMPHASIS_LEVEL__8,
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HTPHY_LINKTYPE_SL1_HT3, //
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0xD5, // Address
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0xC01F06C0, // regData
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0xE01F1FDF, // regMask
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}}
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},
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{
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DeemphasisRegister,
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{
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AMD_FAMILY_10, // CpuFamily
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AMD_F10_C3 // CpuRevision
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},
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{AMD_PF_ALL}, // platformFeatures
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{{
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DEEMPHASIS_LEVEL__11,
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HTPHY_LINKTYPE_SL0_HT3, //
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0xC5, // Address
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0xC01F0DC0, // regData
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0xE01F1FDF, // regMask
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}}
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},
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{
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DeemphasisRegister,
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{
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AMD_FAMILY_10, // CpuFamily
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AMD_F10_C3 // CpuRevision
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},
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{AMD_PF_ALL}, // platformFeatures
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{{
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DEEMPHASIS_LEVEL__11,
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HTPHY_LINKTYPE_SL1_HT3, //
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0xD5, // Address
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0xC01F0DC0, // regData
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0xE01F1FDF, // regMask
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}}
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},
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{
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DeemphasisRegister,
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{
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AMD_FAMILY_10, // CpuFamily
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AMD_F10_C3 // CpuRevision
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},
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{AMD_PF_ALL}, // platformFeatures
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{{
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DEEMPHASIS_LEVEL__11_8,
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HTPHY_LINKTYPE_SL0_HT3, //
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0xC5, // Address
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0xE01F06C7, // regData
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0xE01F1FDF, // regMask
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||||
}}
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},
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{
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DeemphasisRegister,
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{
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AMD_FAMILY_10, // CpuFamily
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AMD_F10_C3 // CpuRevision
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},
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{AMD_PF_ALL}, // platformFeatures
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{{
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DEEMPHASIS_LEVEL__11_8,
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HTPHY_LINKTYPE_SL1_HT3, //
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0xD5, // Address
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0xE01F06C7, // regData
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0xE01F1FDF, // regMask
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}}
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},
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};
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CONST REGISTER_TABLE ROMDATA F10RevCHtPhyRegisterTable = {
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PrimaryCores,
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(sizeof (F10RevCHtPhyRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
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F10RevCHtPhyRegisters
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};
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@ -1,205 +0,0 @@
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/* $NoKeywords:$ */
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* AMD Family_10 HW C1e feature support functions.
|
||||
*
|
||||
* Provides the functions necessary to initialize the hardware C1e feature.
|
||||
*
|
||||
* @xrefitem bom "File Content Label" "Release Content"
|
||||
* @e project: AGESA
|
||||
* @e sub-project: CPU/F10
|
||||
* @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $
|
||||
*
|
||||
*/
|
||||
/*
|
||||
******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2012 Advanced Micro Devices, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* M O D U L E S U S E D
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
#include "AGESA.h"
|
||||
#include "amdlib.h"
|
||||
#include "cpuRegisters.h"
|
||||
#include "cpuHwC1e.h"
|
||||
#include "cpuApicUtilities.h"
|
||||
#include "cpuF10PowerMgmt.h"
|
||||
#include "cpuFamilyTranslation.h"
|
||||
#include "F10PackageType.h"
|
||||
#include "Filecode.h"
|
||||
CODE_GROUP (G1_PEICC)
|
||||
RDATA_GROUP (G2_PEI)
|
||||
#define FILECODE PROC_CPU_FAMILY_0X10_REVC_F10REVCHWC1E_FILECODE
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* D E F I N I T I O N S A N D M A C R O S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* T Y P E D E F S A N D S T R U C T U R E S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
VOID
|
||||
STATIC
|
||||
F10InitializeHwC1eOnCore (
|
||||
IN VOID *IntPendMsr,
|
||||
IN AMD_CONFIG_PARAMS *StdHeader
|
||||
);
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* E X P O R T E D F U N C T I O N S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*---------------------------------------------------------------------------------------*/
|
||||
/**
|
||||
* Should hardware C1e be enabled
|
||||
*
|
||||
* @param[in] HwC1eServices Pointer to this CPU's HW C1e family services.
|
||||
* @param[in] StdHeader Config Handle for library, services.
|
||||
*
|
||||
* @retval TRUE HW C1e is supported.
|
||||
*
|
||||
*/
|
||||
BOOLEAN
|
||||
STATIC
|
||||
F10IsHwC1eSupported (
|
||||
IN HW_C1E_FAMILY_SERVICES *HwC1eServices,
|
||||
IN AMD_CONFIG_PARAMS *StdHeader
|
||||
)
|
||||
{
|
||||
UINT32 PackageType;
|
||||
CPU_LOGICAL_ID LogicalId;
|
||||
|
||||
GetLogicalIdOfCurrentCore (&LogicalId, StdHeader);
|
||||
|
||||
if (((LogicalId.Revision & AMD_F10_RB_ALL) & ~(AMD_F10_RB_C3)) != 0) {
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
// Check if it is BL C2 (not S1g3)
|
||||
if ((LogicalId.Revision & AMD_F10_BL_C2) != 0) {
|
||||
PackageType = LibAmdGetPackageType (StdHeader);
|
||||
if (PackageType != PACKAGE_TYPE_S1G3) {
|
||||
return FALSE;
|
||||
}
|
||||
}
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------------------*/
|
||||
/**
|
||||
* Enable Hardware C1e on a family 10h CPU.
|
||||
*
|
||||
* @param[in] HwC1eServices Pointer to this CPU's HW C1e family services.
|
||||
* @param[in] EntryPoint Timepoint designator.
|
||||
* @param[in] PlatformConfig Contains the runtime modifiable feature input data.
|
||||
* @param[in] StdHeader Config Handle for library, services.
|
||||
*
|
||||
* @return AGESA_SUCCESS Always succeeds.
|
||||
*
|
||||
*/
|
||||
AGESA_STATUS
|
||||
STATIC
|
||||
F10InitializeHwC1e (
|
||||
IN HW_C1E_FAMILY_SERVICES *HwC1eServices,
|
||||
IN UINT64 EntryPoint,
|
||||
IN PLATFORM_CONFIGURATION *PlatformConfig,
|
||||
IN AMD_CONFIG_PARAMS *StdHeader
|
||||
)
|
||||
{
|
||||
UINT32 C1eData;
|
||||
UINT64 LocalMsrRegister;
|
||||
AP_TASK TaskPtr;
|
||||
|
||||
LocalMsrRegister = 0;
|
||||
C1eData = PlatformConfig->C1ePlatformData;
|
||||
|
||||
if (PlatformConfig->C1eMode == C1eModeAuto) {
|
||||
C1eData = PlatformConfig->C1ePlatformData3;
|
||||
}
|
||||
|
||||
((INTPEND_MSR *) &LocalMsrRegister)->IoMsgAddr = C1eData;
|
||||
((INTPEND_MSR *) &LocalMsrRegister)->IoRd = 1;
|
||||
((INTPEND_MSR *) &LocalMsrRegister)->C1eOnCmpHalt = 1;
|
||||
((INTPEND_MSR *) &LocalMsrRegister)->SmiOnCmpHalt = 0;
|
||||
|
||||
TaskPtr.FuncAddress.PfApTaskI = F10InitializeHwC1eOnCore;
|
||||
TaskPtr.DataTransfer.DataSizeInDwords = 2;
|
||||
TaskPtr.DataTransfer.DataPtr = &LocalMsrRegister;
|
||||
TaskPtr.DataTransfer.DataTransferFlags = 0;
|
||||
TaskPtr.ExeFlags = WAIT_FOR_CORE;
|
||||
ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, NULL);
|
||||
|
||||
return AGESA_SUCCESS;
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------------------*/
|
||||
/**
|
||||
* Enable Hardware C1e on a family 10h core.
|
||||
*
|
||||
* @param[in] IntPendMsr MSR value to write to C001_0055 as determined by core 0.
|
||||
* @param[in] StdHeader Config Handle for library, services.
|
||||
*
|
||||
*/
|
||||
VOID
|
||||
STATIC
|
||||
F10InitializeHwC1eOnCore (
|
||||
IN VOID *IntPendMsr,
|
||||
IN AMD_CONFIG_PARAMS *StdHeader
|
||||
)
|
||||
{
|
||||
UINT64 LocalMsrRegister;
|
||||
|
||||
// Enable C1e
|
||||
LibAmdMsrWrite (MSR_INTPEND, (UINT64 *) IntPendMsr, StdHeader);
|
||||
|
||||
// Set OS Visible Workaround Status BIT1 to indicate that C1e
|
||||
// is enabled.
|
||||
LibAmdMsrRead (MSR_OSVW_Status, &LocalMsrRegister, StdHeader);
|
||||
LocalMsrRegister |= BIT1;
|
||||
LibAmdMsrWrite (MSR_OSVW_Status, &LocalMsrRegister, StdHeader);
|
||||
}
|
||||
|
||||
|
||||
CONST HW_C1E_FAMILY_SERVICES ROMDATA F10HwC1e =
|
||||
{
|
||||
0,
|
||||
F10IsHwC1eSupported,
|
||||
F10InitializeHwC1e
|
||||
};
|
||||
|
|
@ -1,133 +0,0 @@
|
|||
/* $NoKeywords:$ */
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* AMD Family_10 Rev C, MSR tables with values as defined in BKDG
|
||||
*
|
||||
* @xrefitem bom "File Content Label" "Release Content"
|
||||
* @e project: AGESA
|
||||
* @e sub-project: CPU
|
||||
* @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $
|
||||
*
|
||||
*/
|
||||
/*
|
||||
******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2012 Advanced Micro Devices, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* M O D U L E S U S E D
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
#include "AGESA.h"
|
||||
#include "cpuRegisters.h"
|
||||
#include "Table.h"
|
||||
#include "Filecode.h"
|
||||
CODE_GROUP (G1_PEICC)
|
||||
RDATA_GROUP (G2_PEI)
|
||||
#define FILECODE PROC_CPU_FAMILY_0X10_REVC_F10REVCMSRTABLES_FILECODE
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* D E F I N I T I O N S A N D M A C R O S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* T Y P E D E F S A N D S T R U C T U R E S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* E X P O R T E D F U N C T I O N S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
STATIC CONST MSR_TYPE_ENTRY_INITIALIZER ROMDATA F10RevCMsrRegisters[] =
|
||||
{
|
||||
// M S R T a b l e s
|
||||
// ----------------------
|
||||
// MSR_LS_CFG (0xC0011020)
|
||||
// bit[1] = 0
|
||||
{
|
||||
MsrRegister,
|
||||
{
|
||||
AMD_FAMILY_10, // CpuFamily
|
||||
AMD_F10_GT_B0 // CpuRevision
|
||||
},
|
||||
{AMD_PF_ALL}, // platformFeatures
|
||||
{{
|
||||
MSR_LS_CFG, // MSR Address
|
||||
0x0000000000000000, // OR Mask
|
||||
(1 << 1), // NAND Mask
|
||||
}}
|
||||
},
|
||||
|
||||
// MSR_BU_CFG (0xC0011023)
|
||||
// bit[21] = 1
|
||||
{
|
||||
MsrRegister,
|
||||
{
|
||||
AMD_FAMILY_10, // CpuFamily
|
||||
AMD_F10_GT_B0 // CpuRevision
|
||||
},
|
||||
{AMD_PF_ALL}, // platformFeatures
|
||||
{{
|
||||
MSR_BU_CFG, // MSR Address
|
||||
(1 << 21), // OR Mask
|
||||
(1 << 21), // NAND Mask
|
||||
}}
|
||||
},
|
||||
|
||||
// MSR_BU_CFG2 (0xC001102A)
|
||||
// bit[50] = 1
|
||||
// For GH rev C1 and later [RdMmExtCfgQwEn]=1
|
||||
{
|
||||
MsrRegister,
|
||||
{
|
||||
AMD_FAMILY_10, // CpuFamily
|
||||
AMD_F10_GT_C0 // CpuRevision
|
||||
},
|
||||
{AMD_PF_ALL}, // platformFeatures
|
||||
{{
|
||||
MSR_BU_CFG2, // MSR Address
|
||||
0x0004000000000000, // OR Mask
|
||||
0x0004000000000000, // NAND Mask
|
||||
}}
|
||||
},
|
||||
};
|
||||
|
||||
CONST REGISTER_TABLE ROMDATA F10RevCMsrRegisterTable = {
|
||||
AllCores,
|
||||
(sizeof (F10RevCMsrRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
|
||||
(TABLE_ENTRY_FIELDS *) &F10RevCMsrRegisters,
|
||||
};
|
||||
|
|
@ -1,265 +0,0 @@
|
|||
/* $NoKeywords:$ */
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* AMD Family_10 Rev C PCI tables with values as defined in BKDG
|
||||
*
|
||||
* @xrefitem bom "File Content Label" "Release Content"
|
||||
* @e project: AGESA
|
||||
* @e sub-project: CPU/FAMILY/0x10/RevC
|
||||
* @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $
|
||||
*
|
||||
*/
|
||||
/*
|
||||
******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2012 Advanced Micro Devices, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* M O D U L E S U S E D
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
#include "AGESA.h"
|
||||
#include "cpuRegisters.h"
|
||||
#include "Table.h"
|
||||
#include "F10PackageType.h"
|
||||
#include "Filecode.h"
|
||||
CODE_GROUP (G1_PEICC)
|
||||
RDATA_GROUP (G2_PEI)
|
||||
#define FILECODE PROC_CPU_FAMILY_0X10_REVC_F10REVCPCITABLES_FILECODE
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* D E F I N I T I O N S A N D M A C R O S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* T Y P E D E F S A N D S T R U C T U R E S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* E X P O R T E D F U N C T I O N S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
// P C I T a b l e s
|
||||
// ----------------------
|
||||
|
||||
STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F10RevCPciRegisters[] =
|
||||
{
|
||||
// Function 2 - DRAM Controller
|
||||
|
||||
// F2x1B0 - Extended Memory Controller Configuration Low Register
|
||||
//
|
||||
// bit[5:4], AdapPrefNegativeStep = 0
|
||||
{
|
||||
PciRegister,
|
||||
{
|
||||
AMD_FAMILY_10, // CpuFamily
|
||||
AMD_F10_Cx // CpuRevision
|
||||
},
|
||||
{AMD_PF_ALL}, // platformFeatures
|
||||
{{
|
||||
MAKE_SBDFO (0, 0, 24, FUNC_2, 0x1B0), // Address
|
||||
0x00000000, // regData
|
||||
0x00000030, // regMask
|
||||
}}
|
||||
},
|
||||
// Function 3 - Misc. Control
|
||||
|
||||
// F3x158 - Link to XCS Token Count
|
||||
// bits[3:0] LnkToXcsDRToken = 3
|
||||
{
|
||||
PciRegister,
|
||||
{
|
||||
AMD_FAMILY_10, // CpuFamily
|
||||
AMD_F10_GT_A2 // CpuRevision
|
||||
},
|
||||
{AMD_PF_UMA}, // platformFeatures
|
||||
{{
|
||||
MAKE_SBDFO (0, 0, 24, FUNC_3, 0x158), // Address
|
||||
0x00000003, // regData
|
||||
0x0000000F, // regMask
|
||||
}}
|
||||
},
|
||||
// F3x80 - ACPI Power State Control
|
||||
// ACPI State C2
|
||||
// bits[0] CpuPrbEn = 1
|
||||
// bits[1] NbLowPwrEn = 0
|
||||
// bits[2] NbGateEn = 0
|
||||
// bits[3] NbCofChg = 0
|
||||
// bits[4] AltVidEn = 0
|
||||
// bits[7:5] ClkDivisor = 1
|
||||
// ACPI State C3, C1E or Link init
|
||||
// bits[0] CpuPrbEn = 0
|
||||
// bits[1] NbLowPwrEn = 1
|
||||
// bits[2] NbGateEn = 1
|
||||
// bits[3] NbCofChg = 0
|
||||
// bits[4] AltVidEn = 0
|
||||
// bits[7:5] ClkDivisor = 7
|
||||
{
|
||||
PciRegister,
|
||||
{
|
||||
AMD_FAMILY_10, // CpuFamily
|
||||
AMD_F10_Cx // CpuRevision
|
||||
},
|
||||
{AMD_PF_ALL}, // platformFeatures
|
||||
{{
|
||||
MAKE_SBDFO (0, 0, 24, FUNC_3, 0x80), // Address
|
||||
0x0000E681, // regData
|
||||
0x0000FFFF, // regMask
|
||||
}}
|
||||
},
|
||||
// F3x80 - ACPI Power State Control
|
||||
// ACPI State C3, C1E or Link init
|
||||
// bits[0] CpuPrbEn = 1
|
||||
// bits[1] NbLowPwrEn = 1
|
||||
// bits[2] NbGateEn = 1
|
||||
// bits[3] NbCofChg = 0
|
||||
// bits[4] AltVidEn = 0
|
||||
// bits[7:5] ClkDivisor = 4
|
||||
{
|
||||
HtFeatPciRegister,
|
||||
{
|
||||
AMD_FAMILY_10, // CpuFamily
|
||||
AMD_F10_Cx // CpuRevision
|
||||
},
|
||||
{AMD_PF_SINGLE_LINK}, // platformFeatures
|
||||
{{
|
||||
HT_HOST_FEAT_HT1, // link feats
|
||||
PACKAGE_TYPE_ASB2, // package type
|
||||
MAKE_SBDFO (0, 0, 24, FUNC_3, 0x80), // Address
|
||||
0x00008700, // regData
|
||||
0x0000FF00, // regMask
|
||||
}}
|
||||
},
|
||||
// F3x80 - ACPI Power State Control
|
||||
// ACPI State C3, C1E or Link init
|
||||
// bits[0] CpuPrbEn = 0
|
||||
// bits[1] NbLowPwrEn = 1
|
||||
// bits[2] NbGateEn = 1
|
||||
// bits[3] NbCofChg = 0
|
||||
// bits[4] AltVidEn = 1
|
||||
// bits[7:5] ClkDivisor = 7
|
||||
{
|
||||
ProfileFixup,
|
||||
{
|
||||
AMD_FAMILY_10, // CpuFamily
|
||||
AMD_F10_C3 // CpuRevision
|
||||
},
|
||||
{AMD_PF_ALL}, // platformFeatures
|
||||
{{
|
||||
PERFORMANCE_VRM_HIGH_SPEED_ENABLE, // PerformanceFeatures
|
||||
MAKE_SBDFO (0, 0, 24, FUNC_3, 0x80), // Address
|
||||
0x0000F600, // regData
|
||||
0x0000FF00, // regMask
|
||||
}}
|
||||
},
|
||||
// F3x80 - ACPI Power State Control
|
||||
// ACPI State C3, C1E or Link init
|
||||
// bits[0] CpuPrbEn = 1
|
||||
// bits[1] NbLowPwrEn = 1
|
||||
// bits[2] NbGateEn = 1
|
||||
// bits[3] NbCofChg = 0
|
||||
// bits[4] AltVidEn = 0
|
||||
// bits[7:5] ClkDivisor = 4
|
||||
{
|
||||
HtFeatPciRegister,
|
||||
{
|
||||
AMD_FAMILY_10, // CpuFamily
|
||||
AMD_F10_Cx // CpuRevision
|
||||
},
|
||||
{AMD_PF_SINGLE_LINK}, // platformFeatures
|
||||
{{
|
||||
HT_HOST_FEAT_HT1, // link feats
|
||||
PACKAGE_TYPE_ALL & (~ PACKAGE_TYPE_ASB2), // package type
|
||||
MAKE_SBDFO (0, 0, 24, FUNC_3, 0x80), // Address
|
||||
0x00008700, // regData
|
||||
0x0000FF00, // regMask
|
||||
}}
|
||||
},
|
||||
// F3xDC - Clock Power Timing Control 2
|
||||
// bits[14:12] NbsynPtrAdj = 5
|
||||
{
|
||||
PciRegister,
|
||||
{
|
||||
AMD_FAMILY_10, // CpuFamily
|
||||
AMD_F10_Cx // CpuRevision
|
||||
},
|
||||
{AMD_PF_ALL}, // platformFeatures
|
||||
{{
|
||||
MAKE_SBDFO (0, 0, 24, FUNC_3, 0xDC), // Address
|
||||
0x00005000, // regData
|
||||
0x00007000, // regMask
|
||||
}}
|
||||
},
|
||||
// F3x180 - NB Extended Configuration
|
||||
// bits[23] SyncFloodOnDramTempErr = 1
|
||||
{
|
||||
PciRegister,
|
||||
{
|
||||
AMD_FAMILY_10, // CpuFamily
|
||||
AMD_F10_Cx // CpuRevision
|
||||
},
|
||||
{AMD_PF_ALL}, // platformFeatures
|
||||
{{
|
||||
MAKE_SBDFO (0, 0, 24, FUNC_3, 0x180), // Address
|
||||
0x00800000, // regData
|
||||
0x00800000, // regMask
|
||||
}}
|
||||
},
|
||||
// F3x188 - NB Extended Configuration Low Register
|
||||
// bit[22] = DisHldReg2
|
||||
// Errata #346
|
||||
{
|
||||
PciRegister,
|
||||
{
|
||||
AMD_FAMILY_10, // CpuFamily
|
||||
AMD_F10_Cx // CpuRevision
|
||||
},
|
||||
{AMD_PF_ALL}, // platformFeatures
|
||||
{{
|
||||
MAKE_SBDFO (0, 0, 24, FUNC_3, 0x188), // Address
|
||||
0x00400000, // regData
|
||||
0x00400000, // regMask
|
||||
}}
|
||||
}
|
||||
};
|
||||
|
||||
CONST REGISTER_TABLE ROMDATA F10RevCPciRegisterTable = {
|
||||
PrimaryCores,
|
||||
(sizeof (F10RevCPciRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
|
||||
F10RevCPciRegisters,
|
||||
};
|
||||
|
|
@ -1,181 +0,0 @@
|
|||
/* $NoKeywords:$ */
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* AMD Family_10 SW C1e feature support functions.
|
||||
*
|
||||
* Provides the functions necessary to initialize the software C1e feature.
|
||||
*
|
||||
* @xrefitem bom "File Content Label" "Release Content"
|
||||
* @e project: AGESA
|
||||
* @e sub-project: CPU/F10
|
||||
* @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $
|
||||
*
|
||||
*/
|
||||
/*
|
||||
******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2012 Advanced Micro Devices, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* M O D U L E S U S E D
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
#include "AGESA.h"
|
||||
#include "amdlib.h"
|
||||
#include "cpuRegisters.h"
|
||||
#include "cpuSwC1e.h"
|
||||
#include "cpuApicUtilities.h"
|
||||
#include "cpuF10PowerMgmt.h"
|
||||
#include "Filecode.h"
|
||||
CODE_GROUP (G1_PEICC)
|
||||
RDATA_GROUP (G2_PEI)
|
||||
#define FILECODE PROC_CPU_FAMILY_0X10_REVC_F10REVCSWC1E_FILECODE
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* D E F I N I T I O N S A N D M A C R O S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* T Y P E D E F S A N D S T R U C T U R E S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
VOID
|
||||
STATIC
|
||||
F10InitializeSwC1eOnCore (
|
||||
IN VOID *IntPendMsr,
|
||||
IN AMD_CONFIG_PARAMS *StdHeader
|
||||
);
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* E X P O R T E D F U N C T I O N S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*---------------------------------------------------------------------------------------*/
|
||||
/**
|
||||
* Should software C1e be enabled
|
||||
*
|
||||
* @param[in] SwC1eServices Pointer to this CPU's SW C1e family services.
|
||||
* @param[in] StdHeader Config Handle for library, services.
|
||||
*
|
||||
* @retval TRUE SW C1e is supported.
|
||||
*
|
||||
*/
|
||||
BOOLEAN
|
||||
STATIC
|
||||
F10IsSwC1eSupported (
|
||||
IN SW_C1E_FAMILY_SERVICES *SwC1eServices,
|
||||
IN AMD_CONFIG_PARAMS *StdHeader
|
||||
)
|
||||
{
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------------------*/
|
||||
/**
|
||||
* Enable Software C1e on a family 10h CPU.
|
||||
*
|
||||
* @param[in] SwC1eServices Pointer to this CPU's SW C1e family services.
|
||||
* @param[in] EntryPoint Timepoint designator.
|
||||
* @param[in] PlatformConfig Contains the runtime modifiable feature input data.
|
||||
* @param[in] StdHeader Config Handle for library, services.
|
||||
*
|
||||
* @return AGESA_SUCCESS Always succeeds.
|
||||
*
|
||||
*/
|
||||
AGESA_STATUS
|
||||
STATIC
|
||||
F10InitializeSwC1e (
|
||||
IN SW_C1E_FAMILY_SERVICES *SwC1eServices,
|
||||
IN UINT64 EntryPoint,
|
||||
IN PLATFORM_CONFIGURATION *PlatformConfig,
|
||||
IN AMD_CONFIG_PARAMS *StdHeader
|
||||
)
|
||||
{
|
||||
UINT64 LocalMsrRegister;
|
||||
AP_TASK TaskPtr;
|
||||
|
||||
LocalMsrRegister = 0;
|
||||
((INTPEND_MSR *) &LocalMsrRegister)->IoMsgAddr = PlatformConfig->C1ePlatformData1;
|
||||
((INTPEND_MSR *) &LocalMsrRegister)->IoMsgData = PlatformConfig->C1ePlatformData2;
|
||||
((INTPEND_MSR *) &LocalMsrRegister)->IoRd = 0;
|
||||
((INTPEND_MSR *) &LocalMsrRegister)->C1eOnCmpHalt = 0;
|
||||
((INTPEND_MSR *) &LocalMsrRegister)->SmiOnCmpHalt = 1;
|
||||
|
||||
TaskPtr.FuncAddress.PfApTaskI = F10InitializeSwC1eOnCore;
|
||||
TaskPtr.DataTransfer.DataSizeInDwords = 2;
|
||||
TaskPtr.DataTransfer.DataPtr = &LocalMsrRegister;
|
||||
TaskPtr.DataTransfer.DataTransferFlags = 0;
|
||||
TaskPtr.ExeFlags = WAIT_FOR_CORE;
|
||||
ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, NULL);
|
||||
|
||||
return AGESA_SUCCESS;
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------------------*/
|
||||
/**
|
||||
* Enable Software C1e on a family 10h core.
|
||||
*
|
||||
* @param[in] IntPendMsr MSR value to write to C001_0055 as determined by core 0.
|
||||
* @param[in] StdHeader Config Handle for library, services.
|
||||
*
|
||||
*/
|
||||
VOID
|
||||
STATIC
|
||||
F10InitializeSwC1eOnCore (
|
||||
IN VOID *IntPendMsr,
|
||||
IN AMD_CONFIG_PARAMS *StdHeader
|
||||
)
|
||||
{
|
||||
UINT64 LocalMsrRegister;
|
||||
|
||||
// Enable C1e
|
||||
LibAmdMsrWrite (MSR_INTPEND, (UINT64 *) IntPendMsr, StdHeader);
|
||||
|
||||
// Set OS Visible Workaround Status BIT1 to indicate that C1e
|
||||
// is enabled.
|
||||
LibAmdMsrRead (MSR_OSVW_Status, &LocalMsrRegister, StdHeader);
|
||||
LocalMsrRegister |= BIT1;
|
||||
LibAmdMsrWrite (MSR_OSVW_Status, &LocalMsrRegister, StdHeader);
|
||||
}
|
||||
|
||||
|
||||
CONST SW_C1E_FAMILY_SERVICES ROMDATA F10SwC1e =
|
||||
{
|
||||
0,
|
||||
F10IsSwC1eSupported,
|
||||
F10InitializeSwC1e
|
||||
};
|
||||
|
|
@ -1,495 +0,0 @@
|
|||
/* $NoKeywords:$ */
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* AMD Family_10 revision Cx specific utility functions.
|
||||
*
|
||||
* Provides numerous utility functions specific to family 10h rev C.
|
||||
*
|
||||
* @xrefitem bom "File Content Label" "Release Content"
|
||||
* @e project: AGESA
|
||||
* @e sub-project: CPU/F10
|
||||
* @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $
|
||||
*
|
||||
*/
|
||||
/*
|
||||
******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2012 Advanced Micro Devices, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* M O D U L E S U S E D
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
#include "AGESA.h"
|
||||
#include "amdlib.h"
|
||||
#include "Ids.h"
|
||||
#include "cpuRegisters.h"
|
||||
#include "cpuFamilyTranslation.h"
|
||||
#include "cpuF10PowerMgmt.h"
|
||||
#include "GeneralServices.h"
|
||||
#include "cpuEarlyInit.h"
|
||||
#include "cpuPostInit.h"
|
||||
#include "cpuFeatures.h"
|
||||
#include "OptionMultiSocket.h"
|
||||
#include "Filecode.h"
|
||||
CODE_GROUP (G1_PEICC)
|
||||
RDATA_GROUP (G2_PEI)
|
||||
#define FILECODE PROC_CPU_FAMILY_0X10_REVC_F10REVCUTILITIES_FILECODE
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* D E F I N I T I O N S A N D M A C R O S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* T Y P E D E F S A N D S T R U C T U R E S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* E X P O R T E D F U N C T I O N S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*---------------------------------------------------------------------------------------*/
|
||||
/**
|
||||
* Set down core register on a revision C processor.
|
||||
*
|
||||
* This function set F3x190 Downcore Control Register[5:0]
|
||||
*
|
||||
* @param[in] FamilySpecificServices The current Family Specific Services.
|
||||
* @param[in] Socket Socket ID.
|
||||
* @param[in] Module Module ID in socket.
|
||||
* @param[in] LeveledCores Number of core.
|
||||
* @param[in] CoreLevelMode Core level mode.
|
||||
* @param[in] StdHeader Header for library and services.
|
||||
*
|
||||
* @retval TRUE Down Core register is updated.
|
||||
* @retval FALSE Down Core register is not updated.
|
||||
*/
|
||||
BOOLEAN
|
||||
F10CommonRevCSetDownCoreRegister (
|
||||
IN CPU_CORE_LEVELING_FAMILY_SERVICES *FamilySpecificServices,
|
||||
IN UINT32 *Socket,
|
||||
IN UINT32 *Module,
|
||||
IN UINT32 *LeveledCores,
|
||||
IN CORE_LEVELING_TYPE CoreLevelMode,
|
||||
IN AMD_CONFIG_PARAMS *StdHeader
|
||||
)
|
||||
{
|
||||
UINT32 TempVar32_a;
|
||||
UINT32 CoreDisableBits;
|
||||
PCI_ADDR PciAddress;
|
||||
BOOLEAN IsUpdated;
|
||||
AGESA_STATUS AgesaStatus;
|
||||
|
||||
IsUpdated = FALSE;
|
||||
|
||||
switch (*LeveledCores) {
|
||||
case 1:
|
||||
CoreDisableBits = DOWNCORE_MASK_SINGLE;
|
||||
break;
|
||||
case 2:
|
||||
CoreDisableBits = DOWNCORE_MASK_DUAL;
|
||||
break;
|
||||
case 3:
|
||||
CoreDisableBits = DOWNCORE_MASK_TRI;
|
||||
break;
|
||||
default:
|
||||
CoreDisableBits = 0;
|
||||
break;
|
||||
}
|
||||
|
||||
if (CoreDisableBits != 0) {
|
||||
if (GetPciAddress (StdHeader, (UINT8) *Socket, (UINT8) *Module, &PciAddress, &AgesaStatus)) {
|
||||
PciAddress.Address.Function = FUNC_3;
|
||||
PciAddress.Address.Register = NORTH_BRIDGE_CAPABILITIES_REG;
|
||||
|
||||
LibAmdPciRead (AccessWidth32, PciAddress, &TempVar32_a, StdHeader);
|
||||
TempVar32_a = (TempVar32_a >> 12) & 0x3;
|
||||
if (TempVar32_a == 0) {
|
||||
CoreDisableBits &= 0x1;
|
||||
} else if (TempVar32_a == 1) {
|
||||
CoreDisableBits &= 0x3;
|
||||
} else if (TempVar32_a == 2) {
|
||||
CoreDisableBits &= 0x7;
|
||||
} else if (TempVar32_a == 3) {
|
||||
CoreDisableBits &= 0x0F;
|
||||
}
|
||||
PciAddress.Address.Register = DOWNCORE_CTRL;
|
||||
LibAmdPciRead (AccessWidth32, PciAddress, &TempVar32_a, StdHeader);
|
||||
if ((TempVar32_a | CoreDisableBits) != TempVar32_a) {
|
||||
TempVar32_a |= CoreDisableBits;
|
||||
LibAmdPciWrite (AccessWidth32, PciAddress, &TempVar32_a, StdHeader);
|
||||
IsUpdated = TRUE;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return IsUpdated;
|
||||
}
|
||||
|
||||
|
||||
CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F10RevCCoreLeveling =
|
||||
{
|
||||
0,
|
||||
F10CommonRevCSetDownCoreRegister
|
||||
};
|
||||
|
||||
|
||||
/*---------------------------------------------------------------------------------------*/
|
||||
/**
|
||||
* Get CPU pstate current on a revision C processor.
|
||||
*
|
||||
* @CpuServiceMethod{::F_CPU_GET_IDD_MAX}.
|
||||
*
|
||||
* This function returns the ProcIddMax.
|
||||
*
|
||||
* @param[in] FamilySpecificServices The current Family Specific Services.
|
||||
* @param[in] Pstate The P-state to check.
|
||||
* @param[out] ProcIddMax P-state current in mA.
|
||||
* @param[in] StdHeader Handle of Header for calling lib functions and services.
|
||||
*
|
||||
* @retval TRUE P-state is enabled
|
||||
* @retval FALSE P-state is disabled
|
||||
*/
|
||||
BOOLEAN
|
||||
F10CommonRevCGetProcIddMax (
|
||||
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
|
||||
IN UINT8 Pstate,
|
||||
OUT UINT32 *ProcIddMax,
|
||||
IN AMD_CONFIG_PARAMS *StdHeader
|
||||
)
|
||||
{
|
||||
UINT32 IddDiv;
|
||||
UINT32 CmpCap;
|
||||
UINT32 LocalPciRegister;
|
||||
UINT32 MsrAddress;
|
||||
UINT32 SinglePlaneNbIdd;
|
||||
UINT64 PstateMsr;
|
||||
BOOLEAN IsPstateEnabled;
|
||||
PCI_ADDR PciAddress;
|
||||
|
||||
IsPstateEnabled = FALSE;
|
||||
|
||||
MsrAddress = (UINT32) (Pstate + PS_REG_BASE);
|
||||
|
||||
ASSERT (MsrAddress <= PS_MAX_REG);
|
||||
|
||||
LibAmdMsrRead (MsrAddress, &PstateMsr, StdHeader);
|
||||
if (((PSTATE_MSR *) &PstateMsr)->PsEnable == 1) {
|
||||
OptionMultiSocketConfiguration.GetCurrPciAddr (&PciAddress, StdHeader);
|
||||
|
||||
PciAddress.Address.Function = FUNC_3;
|
||||
PciAddress.Address.Register = NB_CAPS_REG;
|
||||
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); // F3xE8
|
||||
CmpCap = (UINT32) (((NB_CAPS_REGISTER *) &LocalPciRegister)->CmpCapLo);
|
||||
CmpCap++;
|
||||
|
||||
switch (((PSTATE_MSR *) &PstateMsr)->IddDiv) {
|
||||
case 0:
|
||||
IddDiv = 1000;
|
||||
break;
|
||||
case 1:
|
||||
IddDiv = 100;
|
||||
break;
|
||||
case 2:
|
||||
IddDiv = 10;
|
||||
break;
|
||||
default: // IddDiv = 3 is reserved. Use 10
|
||||
ASSERT (FALSE);
|
||||
IddDiv = 10;
|
||||
break;
|
||||
}
|
||||
|
||||
PciAddress.Address.Register = PW_CTL_MISC_REG;
|
||||
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); // F3xE8
|
||||
if (((POWER_CTRL_MISC_REGISTER *) &LocalPciRegister)->PviMode == 1) {
|
||||
*ProcIddMax = (UINT32) ((PSTATE_MSR *) &PstateMsr)->IddValue * IddDiv * CmpCap;
|
||||
} else {
|
||||
PciAddress.Address.Register = PRCT_INFO_REG;
|
||||
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); // F3xE8
|
||||
SinglePlaneNbIdd = ((PRODUCT_INFO_REGISTER *) &LocalPciRegister)->SinglePlaneNbIdd;
|
||||
SinglePlaneNbIdd <<= 1;
|
||||
*ProcIddMax = ((UINT32) ((PSTATE_MSR *) &PstateMsr)->IddValue * IddDiv * CmpCap) - SinglePlaneNbIdd;
|
||||
}
|
||||
IsPstateEnabled = TRUE;
|
||||
}
|
||||
return IsPstateEnabled;
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------------------*/
|
||||
/**
|
||||
* Returns whether or not BIOS is responsible for configuring the NB COFVID.
|
||||
*
|
||||
* @CpuServiceMethod{::F_CPU_IS_NBCOF_INIT_NEEDED}.
|
||||
*
|
||||
* @param[in] FamilySpecificServices The current Family Specific Services.
|
||||
* @param[in] PciAddress The northbridge to query by pci base address.
|
||||
* @param[out] NbVidUpdateAll Do all NbVids need to be updated
|
||||
* @param[in] StdHeader Header for library and services
|
||||
*
|
||||
* @retval TRUE Perform northbridge frequency and voltage config.
|
||||
* @retval FALSE Do not configure them.
|
||||
*/
|
||||
BOOLEAN
|
||||
F10CommonRevCGetNbCofVidUpdate (
|
||||
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
|
||||
IN PCI_ADDR *PciAddress,
|
||||
OUT BOOLEAN *NbVidUpdateAll,
|
||||
IN AMD_CONFIG_PARAMS *StdHeader
|
||||
)
|
||||
{
|
||||
UINT32 ProductInfoRegister;
|
||||
|
||||
PciAddress->Address.Register = PRCT_INFO_REG;
|
||||
PciAddress->Address.Function = FUNC_3;
|
||||
LibAmdPciRead (AccessWidth32, *PciAddress, &ProductInfoRegister, StdHeader);
|
||||
*NbVidUpdateAll = (BOOLEAN) (((PRODUCT_INFO_REGISTER *) &ProductInfoRegister)->NbVidUpdateAll == 1);
|
||||
return (BOOLEAN) (((PRODUCT_INFO_REGISTER *) &ProductInfoRegister)->NbCofVidUpdate == 1);
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------------------*/
|
||||
/**
|
||||
* Determines the NB clock on the desired node.
|
||||
*
|
||||
* @CpuServiceMethod{::F_CPU_GET_NB_PSTATE_INFO}.
|
||||
*
|
||||
* @param[in] FamilySpecificServices The current Family Specific Services.
|
||||
* @param[in] PlatformConfig Platform profile/build option config structure.
|
||||
* @param[in] PciAddress The segment, bus, and device numbers of the CPU in question.
|
||||
* @param[in] NbPstate The NB P-state number to check.
|
||||
* @param[out] FreqNumeratorInMHz The desired node's frequency numerator in megahertz.
|
||||
* @param[out] FreqDivisor The desired node's frequency divisor.
|
||||
* @param[out] VoltageInuV The desired node's voltage in microvolts.
|
||||
* @param[in] StdHeader Handle of Header for calling lib functions and services.
|
||||
*
|
||||
* @retval TRUE NbPstate is valid
|
||||
* @retval FALSE NbPstate is disabled or invalid
|
||||
*/
|
||||
BOOLEAN
|
||||
F10CommonRevCGetNbPstateInfo (
|
||||
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
|
||||
IN PLATFORM_CONFIGURATION *PlatformConfig,
|
||||
IN PCI_ADDR *PciAddress,
|
||||
IN UINT32 NbPstate,
|
||||
OUT UINT32 *FreqNumeratorInMHz,
|
||||
OUT UINT32 *FreqDivisor,
|
||||
OUT UINT32 *VoltageInuV,
|
||||
IN AMD_CONFIG_PARAMS *StdHeader
|
||||
)
|
||||
{
|
||||
UINT32 NbFid;
|
||||
UINT32 NbVid;
|
||||
UINT32 LocalPciRegister;
|
||||
UINT32 ProductInfoRegister;
|
||||
UINT64 LocalMsrRegister;
|
||||
BOOLEAN PstateIsValid;
|
||||
|
||||
PstateIsValid = TRUE;
|
||||
if (NbPstate == 0) {
|
||||
*FreqDivisor = 1;
|
||||
} else if ((NbPstate == 1) && FamilySpecificServices->IsNbPstateEnabled (FamilySpecificServices, PlatformConfig, StdHeader)) {
|
||||
*FreqDivisor = 2;
|
||||
} else {
|
||||
PstateIsValid = FALSE;
|
||||
}
|
||||
if (PstateIsValid) {
|
||||
PciAddress->Address.Function = FUNC_3;
|
||||
PciAddress->Address.Register = PRCT_INFO_REG;
|
||||
LibAmdPciRead (AccessWidth32, *PciAddress, &ProductInfoRegister, StdHeader);
|
||||
if ((((PRODUCT_INFO_REGISTER *) &ProductInfoRegister)->NbCofVidUpdate) == 0) {
|
||||
PciAddress->Address.Register = CPTC0_REG;
|
||||
LibAmdPciRead (AccessWidth32, *PciAddress, &LocalPciRegister, StdHeader);
|
||||
NbFid = ((CLK_PWR_TIMING_CTRL_REGISTER *) &LocalPciRegister)->NbFid;
|
||||
LibAmdMsrRead (MSR_COFVID_STS, &LocalMsrRegister, StdHeader);
|
||||
NbVid = (UINT32) ((COFVID_STS_MSR *) &LocalMsrRegister)->CurNbVid;
|
||||
} else {
|
||||
NbFid = ((PRODUCT_INFO_REGISTER *) &ProductInfoRegister)->SinglePlaneNbFid;
|
||||
NbVid = ((PRODUCT_INFO_REGISTER *) &ProductInfoRegister)->SinglePlaneNbVid;
|
||||
PciAddress->Address.Register = PW_CTL_MISC_REG;
|
||||
LibAmdPciRead (AccessWidth32, *PciAddress, &LocalPciRegister, StdHeader);
|
||||
if (((POWER_CTRL_MISC_REGISTER *) &LocalPciRegister)->PviMode == 0) {
|
||||
NbFid += ((PRODUCT_INFO_REGISTER *) &ProductInfoRegister)->DualPlaneNbFidOff;
|
||||
NbVid -= ((PRODUCT_INFO_REGISTER *) &ProductInfoRegister)->DualPlaneNbVidOff;
|
||||
}
|
||||
}
|
||||
*FreqNumeratorInMHz = ((NbFid + 4) * 200);
|
||||
*VoltageInuV = (1550000 - (12500 * NbVid));
|
||||
}
|
||||
return PstateIsValid;
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------------------*/
|
||||
/**
|
||||
* Returns the node's minimum and maximum northbridge frequency.
|
||||
*
|
||||
* @CpuServiceMethod{::F_CPU_GET_MIN_MAX_NB_FREQ}.
|
||||
*
|
||||
* @param[in] FamilySpecificServices The current Family Specific Services.
|
||||
* @param[in] PlatformConfig Platform profile/build option config structure.
|
||||
* @param[in] PciAddress The segment, bus, and device numbers of the CPU in question.
|
||||
* @param[out] MinFreqInMHz The node's miminum northbridge frequency.
|
||||
* @param[out] MaxFreqInMHz The node's maximum northbridge frequency.
|
||||
* @param[in] StdHeader Handle of Header for calling lib functions and services.
|
||||
*
|
||||
* @retval AGESA_STATUS Northbridge frequency is valid
|
||||
*/
|
||||
AGESA_STATUS
|
||||
F10RevCGetMinMaxNbFrequency (
|
||||
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
|
||||
IN PLATFORM_CONFIGURATION *PlatformConfig,
|
||||
IN PCI_ADDR *PciAddress,
|
||||
OUT UINT32 *MinFreqInMHz,
|
||||
OUT UINT32 *MaxFreqInMHz,
|
||||
IN AMD_CONFIG_PARAMS *StdHeader
|
||||
)
|
||||
{
|
||||
UINT32 NbPstateEn;
|
||||
UINT32 NbFid;
|
||||
UINT32 FreqDivisor;
|
||||
UINT32 FreqNumerator;
|
||||
UINT32 LocalPciRegister;
|
||||
UINT32 ProductInfoRegister;
|
||||
CPU_LOGICAL_ID LogicalId;
|
||||
|
||||
GetLogicalIdOfCurrentCore (&LogicalId, StdHeader);
|
||||
|
||||
FreqDivisor = 1;
|
||||
|
||||
// If NB P-state is supported, return the frequency of NB P-state 1
|
||||
if ((PlatformConfig->PlatformProfile.PlatformPowerPolicy != Performance) &&
|
||||
((LogicalId.Revision & AMD_F10_C3) != 0)) {
|
||||
PciAddress->Address.Function = FUNC_3;
|
||||
PciAddress->Address.Register = 0x1F0;
|
||||
LibAmdPciReadBits (*PciAddress, 18, 16, &NbPstateEn, StdHeader);
|
||||
|
||||
if (NbPstateEn != 0) {
|
||||
FreqDivisor = 2;
|
||||
}
|
||||
}
|
||||
|
||||
PciAddress->Address.Function = FUNC_3;
|
||||
PciAddress->Address.Register = PRCT_INFO_REG;
|
||||
LibAmdPciRead (AccessWidth32, *PciAddress, &ProductInfoRegister, StdHeader);
|
||||
|
||||
if ((((PRODUCT_INFO_REGISTER *) &ProductInfoRegister)->NbCofVidUpdate) == 0) {
|
||||
PciAddress->Address.Register = CPTC0_REG;
|
||||
LibAmdPciRead (AccessWidth32, *PciAddress, &LocalPciRegister, StdHeader);
|
||||
NbFid = ((CLK_PWR_TIMING_CTRL_REGISTER *) &LocalPciRegister)->NbFid;
|
||||
} else {
|
||||
NbFid = ((PRODUCT_INFO_REGISTER *) &ProductInfoRegister)->SinglePlaneNbFid;
|
||||
PciAddress->Address.Register = PW_CTL_MISC_REG;
|
||||
LibAmdPciRead (AccessWidth32, *PciAddress, &LocalPciRegister, StdHeader);
|
||||
if (((POWER_CTRL_MISC_REGISTER *) &LocalPciRegister)->PviMode == 0) {
|
||||
NbFid += ((PRODUCT_INFO_REGISTER *) &ProductInfoRegister)->DualPlaneNbFidOff;
|
||||
}
|
||||
}
|
||||
|
||||
FreqNumerator = ((NbFid + 4) * 200);
|
||||
*MaxFreqInMHz = FreqNumerator;
|
||||
*MinFreqInMHz = (FreqNumerator / FreqDivisor);
|
||||
|
||||
return AGESA_SUCCESS;
|
||||
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------------------*/
|
||||
/**
|
||||
* Is the Northbridge PState feature enabled?
|
||||
*
|
||||
* @CpuServiceMethod{::F_IS_NB_PSTATE_ENABLED}.
|
||||
*
|
||||
* @param[in] FamilySpecificServices The current Family Specific Services.
|
||||
* @param[in] PlatformConfig Platform profile/build option config structure.
|
||||
* @param[in] StdHeader Handle of Header for calling lib functions and services.
|
||||
*
|
||||
* @retval TRUE The NB PState feature is enabled.
|
||||
* @retval FALSE The NB PState feature is not enabled.
|
||||
*/
|
||||
BOOLEAN
|
||||
F10CommonRevCIsNbPstateEnabled (
|
||||
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
|
||||
IN PLATFORM_CONFIGURATION *PlatformConfig,
|
||||
IN AMD_CONFIG_PARAMS *StdHeader
|
||||
)
|
||||
{
|
||||
UINT32 NbPstate;
|
||||
PCI_ADDR PciAddress;
|
||||
CPU_LOGICAL_ID LogicalId;
|
||||
BOOLEAN Result;
|
||||
|
||||
Result = FALSE;
|
||||
|
||||
GetLogicalIdOfCurrentCore (&LogicalId, StdHeader);
|
||||
if (((LogicalId.Revision & AMD_F10_C3) != 0) && (!IsNonCoherentHt1 (StdHeader))) {
|
||||
OptionMultiSocketConfiguration.GetCurrPciAddr (&PciAddress, StdHeader);
|
||||
PciAddress.Address.Function = FUNC_3;
|
||||
PciAddress.Address.Register = 0x1F0;
|
||||
LibAmdPciReadBits (PciAddress, 18, 16, &NbPstate, StdHeader);
|
||||
if (NbPstate != 0) {
|
||||
Result = TRUE;
|
||||
}
|
||||
}
|
||||
return Result;
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------------------*/
|
||||
/**
|
||||
* Get the number of physical cores of current processor.
|
||||
*
|
||||
* @CpuServiceMethod{::F_CPU_NUMBER_OF_PHYSICAL_CORES}.
|
||||
*
|
||||
* @param[in] FamilySpecificServices The current Family Specific Services.
|
||||
* @param[in] StdHeader Handle of Header for calling lib functions and services.
|
||||
*
|
||||
* @return The number of physical cores.
|
||||
*/
|
||||
UINT8
|
||||
F10CommonRevCGetNumberOfPhysicalCores (
|
||||
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
|
||||
IN AMD_CONFIG_PARAMS *StdHeader
|
||||
)
|
||||
{
|
||||
UINT32 LocalPciRegister;
|
||||
PCI_ADDR PciAddress;
|
||||
|
||||
OptionMultiSocketConfiguration.GetCurrPciAddr (&PciAddress, StdHeader);
|
||||
PciAddress.Address.Function = FUNC_3;
|
||||
PciAddress.Address.Register = NB_CAPS_REG;
|
||||
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
|
||||
return (UINT8) (((NB_CAPS_REGISTER *) &LocalPciRegister)->CmpCapLo + 1);
|
||||
}
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,373 +0,0 @@
|
|||
/* $NoKeywords:$ */
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* AMD Family_10 Rev E HT PCI tables with values as defined in BKDG
|
||||
*
|
||||
* @xrefitem bom "File Content Label" "Release Content"
|
||||
* @e project: AGESA
|
||||
* @e sub-project: CPU/FAMILY/0x10
|
||||
* @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $
|
||||
*
|
||||
*/
|
||||
/*
|
||||
******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2012 Advanced Micro Devices, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* M O D U L E S U S E D
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
#include "AGESA.h"
|
||||
#include "cpuRegisters.h"
|
||||
#include "Table.h"
|
||||
#include "Filecode.h"
|
||||
CODE_GROUP (G1_PEICC)
|
||||
RDATA_GROUP (G2_PEI)
|
||||
|
||||
#define FILECODE PROC_CPU_FAMILY_0X10_REVE_F10REVEHTPHYTABLES_FILECODE
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* D E F I N I T I O N S A N D M A C R O S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* T Y P E D E F S A N D S T R U C T U R E S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* E X P O R T E D F U N C T I O N S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
// HT Phy T a b l e s
|
||||
// -------------------------
|
||||
STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F10RevEHtPhyRegisters[] =
|
||||
{
|
||||
// 0x60:0x68
|
||||
{
|
||||
HtPhyRangeRegister,
|
||||
{
|
||||
AMD_FAMILY_10, // CpuFamily
|
||||
AMD_F10_Ex // CpuRevision
|
||||
},
|
||||
{AMD_PF_ALL}, // platformFeatures
|
||||
{{
|
||||
HTPHY_LINKTYPE_SL0_ALL, //
|
||||
0x60, 0x68, // Address range
|
||||
0x00000040, // regData
|
||||
0x00000040, // regMask
|
||||
}}
|
||||
},
|
||||
// 0x70:0x78
|
||||
{
|
||||
HtPhyRangeRegister,
|
||||
{
|
||||
AMD_FAMILY_10, // CpuFamily
|
||||
AMD_F10_Ex // CpuRevision
|
||||
},
|
||||
{AMD_PF_ALL}, // platformFeatures
|
||||
{{
|
||||
HTPHY_LINKTYPE_SL1_ALL, //
|
||||
0x70, 0x78, // Address range
|
||||
0x00000040, // regData
|
||||
0x00000040, // regMask
|
||||
}}
|
||||
},
|
||||
// 0xC0
|
||||
{
|
||||
HtPhyRegister,
|
||||
{
|
||||
AMD_FAMILY_10, // CpuFamily
|
||||
AMD_F10_Ex // CpuRevision
|
||||
},
|
||||
{AMD_PF_ALL}, // platformFeatures
|
||||
{{
|
||||
HTPHY_LINKTYPE_SL0_ALL, //
|
||||
0xC0, // Address
|
||||
0x40040000, // regData
|
||||
0xe01F0000, // regMask
|
||||
}}
|
||||
},
|
||||
// 0xD0
|
||||
{
|
||||
HtPhyRegister,
|
||||
{
|
||||
AMD_FAMILY_10, // CpuFamily
|
||||
AMD_F10_Ex // CpuRevision
|
||||
},
|
||||
{AMD_PF_ALL}, // platformFeatures
|
||||
{{
|
||||
HTPHY_LINKTYPE_SL1_ALL, //
|
||||
0xD0, // Address
|
||||
0x40040000, // regData
|
||||
0xe01F0000, // regMask
|
||||
}}
|
||||
},
|
||||
// 0x520A
|
||||
{
|
||||
HtPhyRegister,
|
||||
{
|
||||
AMD_FAMILY_10, // CpuFamily
|
||||
AMD_F10_Ex // CpuRevision
|
||||
},
|
||||
{AMD_PF_ALL}, // platformFeatures
|
||||
{{
|
||||
HTPHY_LINKTYPE_SL0_ALL, //
|
||||
0x520A, // Address
|
||||
0x00004000, // regData
|
||||
0x00006000, // regMask
|
||||
}}
|
||||
},
|
||||
// 0x530A
|
||||
{
|
||||
HtPhyRegister,
|
||||
{
|
||||
AMD_FAMILY_10, // CpuFamily
|
||||
AMD_F10_Ex // CpuRevision
|
||||
},
|
||||
{AMD_PF_ALL}, // platformFeatures
|
||||
{{
|
||||
HTPHY_LINKTYPE_SL1_ALL, //
|
||||
0x530A, // Address
|
||||
0x00004000, // regData
|
||||
0x00006000, // regMask
|
||||
}}
|
||||
},
|
||||
|
||||
|
||||
//
|
||||
// Deemphasis Settings
|
||||
//
|
||||
|
||||
// For C3, also set [7]TxLs23ClkGateEn.
|
||||
//deemphasis level DL1[20:16], DL2[12:8], DP1[4:0] PostCur1En[31] PostCur2En[30] PreCur1En[29] MapPostCur2En[6]
|
||||
// No deemphasis 00h 00h 00h 0 0 0 0
|
||||
// -3dB postcursor 12h 00h 00h 1 0 0 0
|
||||
// -6dB postcursor 1Fh 00h 00h 1 0 0 0
|
||||
// -8dB postcursor 1Fh 06h 00h 1 1 0 1
|
||||
// -11dB postcursor 1Fh 0Dh 00h 1 1 0 1
|
||||
// -11dB postcursor with
|
||||
// -8dB precursor 1Fh 06h 07h 1 1 1 1
|
||||
|
||||
{
|
||||
DeemphasisRegister,
|
||||
{
|
||||
AMD_FAMILY_10, // CpuFamily
|
||||
AMD_F10_Ex // CpuRevision
|
||||
},
|
||||
{AMD_PF_ALL}, // platformFeatures
|
||||
{{
|
||||
DEEMPHASIS_LEVEL_NONE,
|
||||
HTPHY_LINKTYPE_SL0_HT3, //
|
||||
0xC5, // Address
|
||||
0x00000080, // regData
|
||||
0xE01F1FDF, // regMask
|
||||
}}
|
||||
},
|
||||
{
|
||||
DeemphasisRegister,
|
||||
{
|
||||
AMD_FAMILY_10, // CpuFamily
|
||||
AMD_F10_Ex // CpuRevision
|
||||
},
|
||||
{AMD_PF_ALL}, // platformFeatures
|
||||
{{
|
||||
DEEMPHASIS_LEVEL_NONE,
|
||||
HTPHY_LINKTYPE_SL1_HT3, //
|
||||
0xD5, // Address
|
||||
0x00000080, // regData
|
||||
0xE01F1FDF, // regMask
|
||||
}}
|
||||
},
|
||||
{
|
||||
DeemphasisRegister,
|
||||
{
|
||||
AMD_FAMILY_10, // CpuFamily
|
||||
AMD_F10_Ex // CpuRevision
|
||||
},
|
||||
{AMD_PF_ALL}, // platformFeatures
|
||||
{{
|
||||
DEEMPHASIS_LEVEL__3,
|
||||
HTPHY_LINKTYPE_SL0_HT3, //
|
||||
0xC5, // Address
|
||||
0x80120080, // regData
|
||||
0xE01F1FDF, // regMask
|
||||
}}
|
||||
},
|
||||
{
|
||||
DeemphasisRegister,
|
||||
{
|
||||
AMD_FAMILY_10, // CpuFamily
|
||||
AMD_F10_Ex // CpuRevision
|
||||
},
|
||||
{AMD_PF_ALL}, // platformFeatures
|
||||
{{
|
||||
DEEMPHASIS_LEVEL__3,
|
||||
HTPHY_LINKTYPE_SL1_HT3, //
|
||||
0xD5, // Address
|
||||
0x80120080, // regData
|
||||
0xE01F1FDF, // regMask
|
||||
}}
|
||||
},
|
||||
{
|
||||
DeemphasisRegister,
|
||||
{
|
||||
AMD_FAMILY_10, // CpuFamily
|
||||
AMD_F10_Ex // CpuRevision
|
||||
},
|
||||
{AMD_PF_ALL}, // platformFeatures
|
||||
{{
|
||||
DEEMPHASIS_LEVEL__6,
|
||||
HTPHY_LINKTYPE_SL0_HT3, //
|
||||
0xC5, // Address
|
||||
0x801F0080, // regData
|
||||
0xE01F1FDF, // regMask
|
||||
}}
|
||||
},
|
||||
{
|
||||
DeemphasisRegister,
|
||||
{
|
||||
AMD_FAMILY_10, // CpuFamily
|
||||
AMD_F10_Ex // CpuRevision
|
||||
},
|
||||
{AMD_PF_ALL}, // platformFeatures
|
||||
{{
|
||||
DEEMPHASIS_LEVEL__6,
|
||||
HTPHY_LINKTYPE_SL1_HT3, //
|
||||
0xD5, // Address
|
||||
0x801F0080, // regData
|
||||
0xE01F1FDF, // regMask
|
||||
}}
|
||||
},
|
||||
{
|
||||
DeemphasisRegister,
|
||||
{
|
||||
AMD_FAMILY_10, // CpuFamily
|
||||
AMD_F10_Ex // CpuRevision
|
||||
},
|
||||
{AMD_PF_ALL}, // platformFeatures
|
||||
{{
|
||||
DEEMPHASIS_LEVEL__8,
|
||||
HTPHY_LINKTYPE_SL0_HT3, //
|
||||
0xC5, // Address
|
||||
0xC01F06C0, // regData
|
||||
0xE01F1FDF, // regMask
|
||||
}}
|
||||
},
|
||||
{
|
||||
DeemphasisRegister,
|
||||
{
|
||||
AMD_FAMILY_10, // CpuFamily
|
||||
AMD_F10_Ex // CpuRevision
|
||||
},
|
||||
{AMD_PF_ALL}, // platformFeatures
|
||||
{{
|
||||
DEEMPHASIS_LEVEL__8,
|
||||
HTPHY_LINKTYPE_SL1_HT3, //
|
||||
0xD5, // Address
|
||||
0xC01F06C0, // regData
|
||||
0xE01F1FDF, // regMask
|
||||
}}
|
||||
},
|
||||
{
|
||||
DeemphasisRegister,
|
||||
{
|
||||
AMD_FAMILY_10, // CpuFamily
|
||||
AMD_F10_Ex // CpuRevision
|
||||
},
|
||||
{AMD_PF_ALL}, // platformFeatures
|
||||
{{
|
||||
DEEMPHASIS_LEVEL__11,
|
||||
HTPHY_LINKTYPE_SL0_HT3, //
|
||||
0xC5, // Address
|
||||
0xC01F0DC0, // regData
|
||||
0xE01F1FDF, // regMask
|
||||
}}
|
||||
},
|
||||
{
|
||||
DeemphasisRegister,
|
||||
{
|
||||
AMD_FAMILY_10, // CpuFamily
|
||||
AMD_F10_Ex // CpuRevision
|
||||
},
|
||||
{AMD_PF_ALL}, // platformFeatures
|
||||
{{
|
||||
DEEMPHASIS_LEVEL__11,
|
||||
HTPHY_LINKTYPE_SL1_HT3, //
|
||||
0xD5, // Address
|
||||
0xC01F0DC0, // regData
|
||||
0xE01F1FDF, // regMask
|
||||
}}
|
||||
},
|
||||
{
|
||||
DeemphasisRegister,
|
||||
{
|
||||
AMD_FAMILY_10, // CpuFamily
|
||||
AMD_F10_Ex // CpuRevision
|
||||
},
|
||||
{AMD_PF_ALL}, // platformFeatures
|
||||
{{
|
||||
DEEMPHASIS_LEVEL__11_8,
|
||||
HTPHY_LINKTYPE_SL0_HT3, //
|
||||
0xC5, // Address
|
||||
0xE01F06C7, // regData
|
||||
0xE01F1FDF, // regMask
|
||||
}}
|
||||
},
|
||||
{
|
||||
DeemphasisRegister,
|
||||
{
|
||||
AMD_FAMILY_10, // CpuFamily
|
||||
AMD_F10_Ex // CpuRevision
|
||||
},
|
||||
{AMD_PF_ALL}, // platformFeatures
|
||||
{{
|
||||
DEEMPHASIS_LEVEL__11_8,
|
||||
HTPHY_LINKTYPE_SL1_HT3, //
|
||||
0xD5, // Address
|
||||
0xE01F06C7, // regData
|
||||
0xE01F1FDF, // regMask
|
||||
}}
|
||||
},
|
||||
};
|
||||
|
||||
CONST REGISTER_TABLE ROMDATA F10RevEHtPhyRegisterTable = {
|
||||
PrimaryCores,
|
||||
(sizeof (F10RevEHtPhyRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
|
||||
F10RevEHtPhyRegisters
|
||||
};
|
||||
|
|
@ -1,134 +0,0 @@
|
|||
/* $NoKeywords:$ */
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* AMD Family_10 Rev E, MSR tables with values as defined in BKDG
|
||||
*
|
||||
* @xrefitem bom "File Content Label" "Release Content"
|
||||
* @e project: AGESA
|
||||
* @e sub-project: CPU
|
||||
* @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $
|
||||
*
|
||||
*/
|
||||
/*
|
||||
******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2012 Advanced Micro Devices, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* M O D U L E S U S E D
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
#include "AGESA.h"
|
||||
#include "cpuRegisters.h"
|
||||
#include "Table.h"
|
||||
#include "Filecode.h"
|
||||
CODE_GROUP (G1_PEICC)
|
||||
RDATA_GROUP (G2_PEI)
|
||||
|
||||
#define FILECODE PROC_CPU_FAMILY_0X10_REVE_F10REVEMSRTABLES_FILECODE
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* D E F I N I T I O N S A N D M A C R O S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* T Y P E D E F S A N D S T R U C T U R E S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* E X P O R T E D F U N C T I O N S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
STATIC CONST MSR_TYPE_ENTRY_INITIALIZER ROMDATA F10RevEMsrRegisters[] =
|
||||
{
|
||||
// M S R T a b l e s
|
||||
// ----------------------
|
||||
// MSR_LS_CFG (0xC0011020)
|
||||
// bit[1] = 0
|
||||
{
|
||||
MsrRegister,
|
||||
{
|
||||
AMD_FAMILY_10, // CpuFamily
|
||||
AMD_F10_Ex // CpuRevision
|
||||
},
|
||||
{AMD_PF_ALL}, // platformFeatures
|
||||
{{
|
||||
MSR_LS_CFG, // MSR Address
|
||||
0x0000000000000000, // OR Mask
|
||||
(1 << 1), // NAND Mask
|
||||
}}
|
||||
},
|
||||
|
||||
// MSR_BU_CFG (0xC0011023)
|
||||
// bit[21] = 1
|
||||
{
|
||||
MsrRegister,
|
||||
{
|
||||
AMD_FAMILY_10, // CpuFamily
|
||||
AMD_F10_Ex // CpuRevision
|
||||
},
|
||||
{AMD_PF_ALL}, // platformFeatures
|
||||
{{
|
||||
MSR_BU_CFG, // MSR Address
|
||||
(1 << 21), // OR Mask
|
||||
(1 << 21), // NAND Mask
|
||||
}}
|
||||
},
|
||||
|
||||
// MSR_BU_CFG2 (0xC001102A)
|
||||
// bit[50] = 1
|
||||
// For GH rev C1 and later [RdMmExtCfgQwEn]=1
|
||||
{
|
||||
MsrRegister,
|
||||
{
|
||||
AMD_FAMILY_10, // CpuFamily
|
||||
AMD_F10_Ex // CpuRevision
|
||||
},
|
||||
{AMD_PF_ALL}, // platformFeatures
|
||||
{{
|
||||
MSR_BU_CFG2, // MSR Address
|
||||
0x0004000000000000, // OR Mask
|
||||
0x0004000000000000, // NAND Mask
|
||||
}}
|
||||
},
|
||||
};
|
||||
|
||||
CONST REGISTER_TABLE ROMDATA F10RevEMsrRegisterTable = {
|
||||
AllCores,
|
||||
(sizeof (F10RevEMsrRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
|
||||
(TABLE_ENTRY_FIELDS *) &F10RevEMsrRegisters,
|
||||
};
|
||||
|
|
@ -1,225 +0,0 @@
|
|||
/* $NoKeywords:$ */
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* AMD Family_10 Rev E PCI tables with values as defined in BKDG
|
||||
*
|
||||
* @xrefitem bom "File Content Label" "Release Content"
|
||||
* @e project: AGESA
|
||||
* @e sub-project: CPU/FAMILY/0x10/RevE
|
||||
* @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $
|
||||
*
|
||||
*/
|
||||
/*
|
||||
******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2012 Advanced Micro Devices, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* M O D U L E S U S E D
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
#include "AGESA.h"
|
||||
#include "cpuRegisters.h"
|
||||
#include "Table.h"
|
||||
#include "Filecode.h"
|
||||
CODE_GROUP (G1_PEICC)
|
||||
RDATA_GROUP (G2_PEI)
|
||||
|
||||
#define FILECODE PROC_CPU_FAMILY_0X10_REVE_F10REVEPCITABLES_FILECODE
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* D E F I N I T I O N S A N D M A C R O S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* T Y P E D E F S A N D S T R U C T U R E S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* E X P O R T E D F U N C T I O N S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
// P C I T a b l e s
|
||||
// ----------------------
|
||||
|
||||
STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F10RevEPciRegisters[] =
|
||||
{
|
||||
// F0x68 -
|
||||
// BufRelPri for rev E
|
||||
// bits[14:13] BufRelPri = 1
|
||||
{
|
||||
PciRegister,
|
||||
{
|
||||
AMD_FAMILY_10, // CpuFamily
|
||||
AMD_F10_Ex // CpuRevision
|
||||
},
|
||||
{AMD_PF_ALL}, // platformFeatures
|
||||
{{
|
||||
MAKE_SBDFO(0, 0, 24, FUNC_0, 0x68), // Address
|
||||
0x00002000, // regData
|
||||
0x00006000, // regMask
|
||||
}}
|
||||
},
|
||||
|
||||
// F0x16C - Link Global Extended Control Register
|
||||
// bit[7:6] InLnSt = 0x01
|
||||
{
|
||||
PciRegister,
|
||||
{
|
||||
AMD_FAMILY_10, // CpuFamily
|
||||
AMD_F10_Ex // CpuRevision
|
||||
},
|
||||
{AMD_PF_SINGLE_LINK}, // platformFeatures
|
||||
{{
|
||||
MAKE_SBDFO (0, 0, 24, FUNC_0, 0x16C), // Address
|
||||
0x0000C026, // regData
|
||||
0x0000E03F, // regMask
|
||||
}}
|
||||
},
|
||||
// F0x16C - Link Global Extended Control Register
|
||||
// bit[15:13] ForceFullT0 = 6
|
||||
// bit[9] RXCalEn = 1
|
||||
// bit[5:0] T0Time = 0x26
|
||||
{
|
||||
PciRegister,
|
||||
{
|
||||
AMD_FAMILY_10, // CpuFamily
|
||||
AMD_F10_Ex // CpuRevision
|
||||
},
|
||||
{AMD_PF_SINGLE_LINK}, // platformFeatures
|
||||
{{
|
||||
MAKE_SBDFO (0, 0, 24, FUNC_0, 0x16C), // Address
|
||||
0x0000C226, // regData
|
||||
0x0000E23F, // regMask
|
||||
}}
|
||||
},
|
||||
// F3x80 - ACPI Power State Control
|
||||
// ACPI State C2
|
||||
// bits[0] CpuPrbEn = 1
|
||||
// bits[1] NbLowPwrEn = 0
|
||||
// bits[2] NbGateEn = 0
|
||||
// bits[3] NbCofChg = 0
|
||||
// bits[4] AltVidEn = 0
|
||||
// bits[7:5] ClkDivisor = 1
|
||||
// ACPI State C3, C1E or Link init
|
||||
// bits[0] CpuPrbEn = 0
|
||||
// bits[1] NbLowPwrEn = 1
|
||||
// bits[2] NbGateEn = 1
|
||||
// bits[3] NbCofChg = 0
|
||||
// bits[4] AltVidEn = 0
|
||||
// bits[7:5] ClkDivisor = 7
|
||||
{
|
||||
PciRegister,
|
||||
{
|
||||
AMD_FAMILY_10, // CpuFamily
|
||||
AMD_F10_Ex // CpuRevision
|
||||
},
|
||||
{AMD_PF_ALL}, // platformFeatures
|
||||
{{
|
||||
MAKE_SBDFO (0, 0, 24, FUNC_3, 0x80), // Address
|
||||
0x0000E681, // regData
|
||||
0x0000FFFF, // regMask
|
||||
}}
|
||||
},
|
||||
// F3xDC - Clock Power Timing Control 2
|
||||
// bits[14:12] NbsynPtrAdj = 6
|
||||
{
|
||||
PciRegister,
|
||||
{
|
||||
AMD_FAMILY_10, // CpuFamily
|
||||
AMD_F10_Ex // CpuRevision
|
||||
},
|
||||
{AMD_PF_ALL}, // platformFeatures
|
||||
{{
|
||||
MAKE_SBDFO (0, 0, 24, FUNC_3, 0xDC), // Address
|
||||
0x00006000, // regData
|
||||
0x00007000, // regMask
|
||||
}}
|
||||
},
|
||||
// F3x1C4 - L3 Power Control Register
|
||||
// bits[8] L3PwrSavEn = 1
|
||||
{
|
||||
PciRegister,
|
||||
{
|
||||
AMD_FAMILY_10, // CpuFamily
|
||||
AMD_F10_Ex // CpuRevision
|
||||
},
|
||||
{AMD_PF_ALL}, // platformFeatures
|
||||
{{
|
||||
MAKE_SBDFO (0, 0, 24, FUNC_4, 0x1C4), // Address
|
||||
0x00000100, // regData
|
||||
0x00000100, // regMask
|
||||
}}
|
||||
},
|
||||
// F3x188 - NB Extended Configuration Low Register
|
||||
// bit[4] = EnStpGntOnFlushMaskWakeup
|
||||
{
|
||||
PciRegister,
|
||||
{
|
||||
AMD_FAMILY_10, // CpuFamily
|
||||
AMD_F10_Ex // CpuRevision
|
||||
},
|
||||
{AMD_PF_ALL}, // platformFeatures
|
||||
{{
|
||||
MAKE_SBDFO (0, 0, 24, FUNC_3, 0x188), // Address
|
||||
0x00000010, // regData
|
||||
0x00000010, // regMask
|
||||
}}
|
||||
},
|
||||
// F4x15C - Core Performance Boost Control
|
||||
// bits[1:0] BoostSrc = 0
|
||||
{
|
||||
PciRegister,
|
||||
{
|
||||
AMD_FAMILY_10, // CpuFamily
|
||||
AMD_F10_Ex // CpuRevision
|
||||
},
|
||||
{AMD_PF_ALL}, // platformFeatures
|
||||
{{
|
||||
MAKE_SBDFO (0, 0, 24, FUNC_4, 0x15C), // Address
|
||||
0x00000000, // regData
|
||||
0x00000003, // regMask
|
||||
}}
|
||||
},
|
||||
};
|
||||
|
||||
CONST REGISTER_TABLE ROMDATA F10RevEPciRegisterTable = {
|
||||
PrimaryCores,
|
||||
(sizeof (F10RevEPciRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
|
||||
F10RevEPciRegisters,
|
||||
};
|
||||
|
|
@ -1,396 +0,0 @@
|
|||
/* $NoKeywords:$ */
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* AMD Family_10 revision Ex specific utility functions.
|
||||
*
|
||||
* Provides numerous utility functions specific to family 10h rev E.
|
||||
*
|
||||
* @xrefitem bom "File Content Label" "Release Content"
|
||||
* @e project: AGESA
|
||||
* @e sub-project: CPU/F10
|
||||
* @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $
|
||||
*
|
||||
*/
|
||||
/*
|
||||
******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2012 Advanced Micro Devices, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* M O D U L E S U S E D
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
#include "AGESA.h"
|
||||
#include "amdlib.h"
|
||||
#include "Ids.h"
|
||||
#include "cpuRegisters.h"
|
||||
#include "cpuFamilyTranslation.h"
|
||||
#include "cpuF10PowerMgmt.h"
|
||||
#include "GeneralServices.h"
|
||||
#include "cpuEarlyInit.h"
|
||||
#include "cpuRegisters.h"
|
||||
#include "OptionMultiSocket.h"
|
||||
#include "Filecode.h"
|
||||
CODE_GROUP (G1_PEICC)
|
||||
RDATA_GROUP (G2_PEI)
|
||||
|
||||
#define FILECODE PROC_CPU_FAMILY_0X10_REVE_F10REVEUTILITIES_FILECODE
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* D E F I N I T I O N S A N D M A C R O S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* T Y P E D E F S A N D S T R U C T U R E S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------------------
|
||||
* E X P O R T E D F U N C T I O N S
|
||||
*----------------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*---------------------------------------------------------------------------------------*/
|
||||
/**
|
||||
* Set down core register on a revision E processor.
|
||||
*
|
||||
* This function set F3x190 Downcore Control Register[5:0]
|
||||
*
|
||||
* @param[in] FamilySpecificServices The current Family Specific Services.
|
||||
* @param[in] Socket Socket ID.
|
||||
* @param[in] Module Module ID in socket.
|
||||
* @param[in] LeveledCores Number of core.
|
||||
* @param[in] CoreLevelMode Core level mode.
|
||||
* @param[in] StdHeader Header for library and services.
|
||||
*
|
||||
* @retval TRUE Down Core register is updated.
|
||||
* @retval FALSE Down Core register is not updated.
|
||||
*/
|
||||
BOOLEAN
|
||||
F10CommonRevESetDownCoreRegister (
|
||||
IN CPU_CORE_LEVELING_FAMILY_SERVICES *FamilySpecificServices,
|
||||
IN UINT32 *Socket,
|
||||
IN UINT32 *Module,
|
||||
IN UINT32 *LeveledCores,
|
||||
IN CORE_LEVELING_TYPE CoreLevelMode,
|
||||
IN AMD_CONFIG_PARAMS *StdHeader
|
||||
)
|
||||
{
|
||||
UINT32 TempVar32_a;
|
||||
UINT32 CoreDisableBits;
|
||||
PCI_ADDR PciAddress;
|
||||
BOOLEAN IsUpdated;
|
||||
AGESA_STATUS AgesaStatus;
|
||||
|
||||
IsUpdated = FALSE;
|
||||
|
||||
switch (*LeveledCores) {
|
||||
case 1:
|
||||
CoreDisableBits = DOWNCORE_MASK_SINGLE;
|
||||
break;
|
||||
case 2:
|
||||
CoreDisableBits = DOWNCORE_MASK_DUAL;
|
||||
break;
|
||||
case 3:
|
||||
CoreDisableBits = DOWNCORE_MASK_TRI;
|
||||
break;
|
||||
case 4:
|
||||
CoreDisableBits = DOWNCORE_MASK_FOUR;
|
||||
break;
|
||||
case 5:
|
||||
CoreDisableBits = DOWNCORE_MASK_FIVE;
|
||||
break;
|
||||
default:
|
||||
CoreDisableBits = 0;
|
||||
break;
|
||||
}
|
||||
|
||||
if (CoreDisableBits != 0) {
|
||||
if (GetPciAddress (StdHeader, (UINT8) *Socket, (UINT8) *Module, &PciAddress, &AgesaStatus)) {
|
||||
PciAddress.Address.Function = FUNC_3;
|
||||
PciAddress.Address.Register = NORTH_BRIDGE_CAPABILITIES_REG;
|
||||
|
||||
LibAmdPciRead (AccessWidth32, PciAddress, &TempVar32_a, StdHeader);
|
||||
TempVar32_a = ((TempVar32_a >> 12) & 0x3) | ((TempVar32_a >> 13) & 0x4);
|
||||
if (TempVar32_a == 0) {
|
||||
CoreDisableBits &= 0x1;
|
||||
} else if (TempVar32_a == 1) {
|
||||
CoreDisableBits &= 0x3;
|
||||
} else if (TempVar32_a == 2) {
|
||||
CoreDisableBits &= 0x7;
|
||||
} else if (TempVar32_a == 3) {
|
||||
CoreDisableBits &= 0x0F;
|
||||
} else if (TempVar32_a == 4) {
|
||||
CoreDisableBits &= 0x1F;
|
||||
} else if (TempVar32_a == 5) {
|
||||
CoreDisableBits &= 0x3F;
|
||||
}
|
||||
PciAddress.Address.Register = DOWNCORE_CTRL;
|
||||
LibAmdPciRead (AccessWidth32, PciAddress, &TempVar32_a, StdHeader);
|
||||
if ((TempVar32_a | CoreDisableBits) != TempVar32_a) {
|
||||
TempVar32_a |= CoreDisableBits;
|
||||
LibAmdPciWrite (AccessWidth32, PciAddress, &TempVar32_a, StdHeader);
|
||||
IsUpdated = TRUE;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return IsUpdated;
|
||||
}
|
||||
|
||||
|
||||
CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F10RevECoreLeveling =
|
||||
{
|
||||
0,
|
||||
F10CommonRevESetDownCoreRegister
|
||||
};
|
||||
|
||||
/*---------------------------------------------------------------------------------------*/
|
||||
/**
|
||||
* Get CPU pstate current on a revision E processor.
|
||||
*
|
||||
* @CpuServiceMethod{::F_CPU_GET_IDD_MAX}.
|
||||
*
|
||||
* This function returns the ProcIddMax.
|
||||
*
|
||||
* @param[in] FamilySpecificServices The current Family Specific Services.
|
||||
* @param[in] Pstate The P-state to check.
|
||||
* @param[out] ProcIddMax P-state current in mA.
|
||||
* @param[in] StdHeader Handle of Header for calling lib functions and services.
|
||||
*
|
||||
* @retval TRUE P-state is enabled
|
||||
* @retval FALSE P-state is disabled
|
||||
*/
|
||||
BOOLEAN
|
||||
F10CommonRevEGetProcIddMax (
|
||||
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
|
||||
IN UINT8 Pstate,
|
||||
OUT UINT32 *ProcIddMax,
|
||||
IN AMD_CONFIG_PARAMS *StdHeader
|
||||
)
|
||||
{
|
||||
UINT32 IddDiv;
|
||||
UINT32 CmpCap;
|
||||
UINT32 LocalPciRegister;
|
||||
UINT32 MsrAddress;
|
||||
UINT32 MultiNodeCpu;
|
||||
UINT64 PstateMsr;
|
||||
BOOLEAN IsPstateEnabled;
|
||||
PCI_ADDR PciAddress;
|
||||
|
||||
IsPstateEnabled = FALSE;
|
||||
|
||||
MsrAddress = (UINT32) (Pstate + PS_REG_BASE);
|
||||
ASSERT (MsrAddress <= PS_MAX_REG);
|
||||
|
||||
LibAmdMsrRead (MsrAddress, &PstateMsr, StdHeader);
|
||||
if (((PSTATE_MSR *) &PstateMsr)->PsEnable == 1) {
|
||||
OptionMultiSocketConfiguration.GetCurrPciAddr (&PciAddress, StdHeader);
|
||||
|
||||
PciAddress.Address.Function = FUNC_3;
|
||||
PciAddress.Address.Register = NB_CAPS_REG;
|
||||
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader); // F3xE8
|
||||
|
||||
switch (((PSTATE_MSR *) &PstateMsr)->IddDiv) {
|
||||
case 0:
|
||||
IddDiv = 1000;
|
||||
break;
|
||||
case 1:
|
||||
IddDiv = 100;
|
||||
break;
|
||||
case 2:
|
||||
IddDiv = 10;
|
||||
break;
|
||||
default: // IddDiv = 3 is reserved. Use 10
|
||||
ASSERT (FALSE);
|
||||
IddDiv = 10;
|
||||
break;
|
||||
}
|
||||
MultiNodeCpu = (UINT32) (((NB_CAPS_REGISTER *) &LocalPciRegister)->MultiNodeCpu + 1);
|
||||
CmpCap = (UINT32) (((NB_CAPS_REGISTER *) &LocalPciRegister)->CmpCapHi << 2);
|
||||
CmpCap |= (UINT32) (((NB_CAPS_REGISTER *) &LocalPciRegister)->CmpCapLo);
|
||||
CmpCap++;
|
||||
*ProcIddMax = (UINT32) ((PSTATE_MSR *) &PstateMsr)->IddValue * IddDiv * CmpCap * MultiNodeCpu;
|
||||
IsPstateEnabled = TRUE;
|
||||
}
|
||||
return IsPstateEnabled;
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------------------*/
|
||||
/**
|
||||
* Determines the NB clock on the desired node.
|
||||
*
|
||||
* @CpuServiceMethod{::F_CPU_GET_NB_PSTATE_INFO}.
|
||||
*
|
||||
* @param[in] FamilySpecificServices The current Family Specific Services.
|
||||
* @param[in] PlatformConfig Platform profile/build option config structure.
|
||||
* @param[in] PciAddress The segment, bus, and device numbers of the CPU in question.
|
||||
* @param[in] NbPstate The NB P-state number to check.
|
||||
* @param[out] FreqNumeratorInMHz The desired node's frequency numerator in megahertz.
|
||||
* @param[out] FreqDivisor The desired node's frequency divisor.
|
||||
* @param[out] VoltageInuV The desired node's voltage in microvolts.
|
||||
* @param[in] StdHeader Handle of Header for calling lib functions and services.
|
||||
*
|
||||
* @retval TRUE NbPstate is valid
|
||||
* @retval FALSE NbPstate is disabled or invalid
|
||||
*/
|
||||
BOOLEAN
|
||||
F10CommonRevEGetNbPstateInfo (
|
||||
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
|
||||
IN PLATFORM_CONFIGURATION *PlatformConfig,
|
||||
IN PCI_ADDR *PciAddress,
|
||||
IN UINT32 NbPstate,
|
||||
OUT UINT32 *FreqNumeratorInMHz,
|
||||
OUT UINT32 *FreqDivisor,
|
||||
OUT UINT32 *VoltageInuV,
|
||||
IN AMD_CONFIG_PARAMS *StdHeader
|
||||
)
|
||||
{
|
||||
UINT32 LocalPciRegister;
|
||||
UINT64 LocalMsrRegister;
|
||||
BOOLEAN PstateIsValid;
|
||||
|
||||
PstateIsValid = FALSE;
|
||||
if (NbPstate == 0) {
|
||||
PciAddress->Address.Function = FUNC_3;
|
||||
PciAddress->Address.Register = CPTC0_REG;
|
||||
LibAmdPciRead (AccessWidth32, *PciAddress, &LocalPciRegister, StdHeader);
|
||||
*FreqNumeratorInMHz = ((((CLK_PWR_TIMING_CTRL_REGISTER *) &LocalPciRegister)->NbFid + 4) * 200);
|
||||
*FreqDivisor = 1;
|
||||
LibAmdMsrRead (MSR_COFVID_STS, &LocalMsrRegister, StdHeader);
|
||||
*VoltageInuV = (1550000 - (12500 * ((UINT32) ((COFVID_STS_MSR *) &LocalMsrRegister)->CurNbVid)));
|
||||
PstateIsValid = TRUE;
|
||||
}
|
||||
return PstateIsValid;
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------------------*/
|
||||
/**
|
||||
* Returns the node's minimum and maximum northbridge frequency.
|
||||
*
|
||||
* @CpuServiceMethod{::F_CPU_GET_MIN_MAX_NB_FREQ}.
|
||||
*
|
||||
* @param[in] FamilySpecificServices The current Family Specific Services.
|
||||
* @param[in] PlatformConfig Platform profile/build option config structure.
|
||||
* @param[in] PciAddress The segment, bus, and device numbers of the CPU in question.
|
||||
* @param[out] MinFreqInMHz The node's minimum northbridge frequency.
|
||||
* @param[out] MaxFreqInMHz The node's maximum northbridge frequency.
|
||||
* @param[in] StdHeader Handle of Header for calling lib functions and services.
|
||||
*
|
||||
* @retval AGESA_STATUS Northbridge frequency is valid
|
||||
*/
|
||||
AGESA_STATUS
|
||||
F10RevEGetMinMaxNbFrequency (
|
||||
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
|
||||
IN PLATFORM_CONFIGURATION *PlatformConfig,
|
||||
IN PCI_ADDR *PciAddress,
|
||||
OUT UINT32 *MinFreqInMHz,
|
||||
OUT UINT32 *MaxFreqInMHz,
|
||||
IN AMD_CONFIG_PARAMS *StdHeader
|
||||
)
|
||||
{
|
||||
UINT32 LocalPciRegister;
|
||||
|
||||
PciAddress->Address.Function = FUNC_3;
|
||||
PciAddress->Address.Register = CPTC0_REG;
|
||||
LibAmdPciRead (AccessWidth32, *PciAddress, &LocalPciRegister, StdHeader);
|
||||
*MinFreqInMHz = ((((CLK_PWR_TIMING_CTRL_REGISTER *) &LocalPciRegister)->NbFid + 4) * 200);
|
||||
*MaxFreqInMHz = *MinFreqInMHz;
|
||||
|
||||
return AGESA_SUCCESS;
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------------------*/
|
||||
/**
|
||||
* Returns whether or not BIOS is responsible for configuring the NB COFVID.
|
||||
*
|
||||
* @CpuServiceMethod{::F_CPU_IS_NBCOF_INIT_NEEDED}.
|
||||
*
|
||||
* @param[in] FamilySpecificServices The current Family Specific Services.
|
||||
* @param[in] PciAddress The northbridge to query by pci base address.
|
||||
* @param[out] NbVidUpdateAll Do all NbVids need to be updated
|
||||
* @param[in] StdHeader Header for library and services
|
||||
*
|
||||
* @retval TRUE Perform northbridge frequency and voltage config.
|
||||
* @retval FALSE Do not configure them.
|
||||
*/
|
||||
BOOLEAN
|
||||
F10CommonRevEGetNbCofVidUpdate (
|
||||
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
|
||||
IN PCI_ADDR *PciAddress,
|
||||
OUT BOOLEAN *NbVidUpdateAll,
|
||||
IN AMD_CONFIG_PARAMS *StdHeader
|
||||
)
|
||||
{
|
||||
UINT32 ProductInfoRegister;
|
||||
|
||||
PciAddress->Address.Register = PRCT_INFO_REG;
|
||||
PciAddress->Address.Function = FUNC_3;
|
||||
LibAmdPciRead (AccessWidth32, *PciAddress, &ProductInfoRegister, StdHeader);
|
||||
*NbVidUpdateAll = (BOOLEAN) (((PRODUCT_INFO_REGISTER *) &ProductInfoRegister)->NbVidUpdateAll == 1);
|
||||
return (BOOLEAN) (((PRODUCT_INFO_REGISTER *) &ProductInfoRegister)->NbCofVidUpdate == 1);
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------------------*/
|
||||
/**
|
||||
* Get the number of physical cores of current processor.
|
||||
*
|
||||
* @CpuServiceMethod{::F_CPU_NUMBER_OF_PHYSICAL_CORES}.
|
||||
*
|
||||
* @param[in] FamilySpecificServices The current Family Specific Services.
|
||||
* @param[in] StdHeader Handle of Header for calling lib functions and services.
|
||||
*
|
||||
* @return The number of physical cores.
|
||||
*/
|
||||
UINT8
|
||||
F10CommonRevEGetNumberOfPhysicalCores (
|
||||
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
|
||||
IN AMD_CONFIG_PARAMS *StdHeader
|
||||
)
|
||||
{
|
||||
UINT32 CmpCap;
|
||||
UINT32 LocalPciRegister;
|
||||
PCI_ADDR PciAddress;
|
||||
|
||||
OptionMultiSocketConfiguration.GetCurrPciAddr (&PciAddress, StdHeader);
|
||||
PciAddress.Address.Function = FUNC_3;
|
||||
PciAddress.Address.Register = NB_CAPS_REG;
|
||||
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
|
||||
CmpCap = (UINT8) (((NB_CAPS_REGISTER *) &LocalPciRegister)->CmpCapHi << 2);
|
||||
CmpCap |= (UINT8) (((NB_CAPS_REGISTER *) &LocalPciRegister)->CmpCapLo);
|
||||
|
||||
return (UINT8) (CmpCap + 1);
|
||||
}
|
||||
|
|
@ -1,223 +0,0 @@
|
|||
/* $NoKeywords:$ */
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* mpSorA3.c
|
||||
*
|
||||
* Platform specific settings for OR AM3 DDR3 SO-DIMM system
|
||||
*
|
||||
* @xrefitem bom "File Content Label" "Release Content"
|
||||
* @e project: AGESA
|
||||
* @e sub-project: (Mem/Ps/OR/AM3)
|
||||
* @e \$Revision: 50871 $ @e \$Date: 2011-04-14 15:39:51 -0600 (Thu, 14 Apr 2011) $
|
||||
*
|
||||
**/
|
||||
/*****************************************************************************
|
||||
*
|
||||
* Copyright (C) 2012 Advanced Micro Devices, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* ***************************************************************************
|
||||
*
|
||||
*/
|
||||
|
||||
#include "AGESA.h"
|
||||
#include "AdvancedApi.h"
|
||||
#include "ma.h"
|
||||
#include "Ids.h"
|
||||
#include "cpuFamRegisters.h"
|
||||
#include "cpuRegisters.h"
|
||||
#include "mm.h"
|
||||
#include "mn.h"
|
||||
#include "mp.h"
|
||||
#include "mu.h"
|
||||
#include "PlatformMemoryConfiguration.h"
|
||||
#include "Filecode.h"
|
||||
CODE_GROUP (G2_PEI)
|
||||
RDATA_GROUP (G2_PEI)
|
||||
|
||||
#define FILECODE PROC_MEM_PS_OR_AM3_MPSORA3_FILECODE
|
||||
/*----------------------------------------------------------------------------
|
||||
* DEFINITIONS AND MACROS
|
||||
*
|
||||
*----------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
* TYPEDEFS AND STRUCTURES
|
||||
*
|
||||
*----------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
* PROTOTYPES OF LOCAL FUNCTIONS
|
||||
*
|
||||
*----------------------------------------------------------------------------
|
||||
*/
|
||||
/*
|
||||
*-----------------------------------------------------------------------------
|
||||
* EXPORTED FUNCTIONS
|
||||
*
|
||||
*-----------------------------------------------------------------------------
|
||||
*/
|
||||
// Slow mode, Address timing and Output drive compensation
|
||||
// Format :
|
||||
// DimmPerCh, DDRrate, VDDIO, Dimm0, Dimm1, Dimm2, SlowMode, AddTmgCtl, ODC
|
||||
//
|
||||
STATIC CONST PSCFG_SAO_ENTRY OrAM3SODdr3SAO[] = {
|
||||
{1, DDR667 + DDR800, V1_5, DIMM_SR, NP, NP, 0, 0x00000000, 0x00112222},
|
||||
{1, DDR667 + DDR800, V1_5, DIMM_DR, NP, NP, 0, 0x003B0000, 0x00112222},
|
||||
{1, DDR1066, V1_5, DIMM_SR, NP, NP, 0, 0x00000000, 0x10112222},
|
||||
{1, DDR1066, V1_5, DIMM_DR, NP, NP, 0, 0x00380000, 0x10112222},
|
||||
{1, DDR1333, V1_5, DIMM_SR, NP, NP, 0, 0x00000000, 0x20112222},
|
||||
{1, DDR1333, V1_5, DIMM_DR, NP, NP, 0, 0x00360000, 0x20112222},
|
||||
{1, DDR1600 + DDR1866, V1_5, DIMM_SR, NP, NP, 0, 0x00000000, 0x30112222},
|
||||
{1, DDR1600 + DDR1866, V1_5, DIMM_DR, NP, NP, 1, 0x00000000, 0x30112222},
|
||||
{2, DDR667 + DDR800, V1_5, NP, DIMM_SR, NP, 0, 0x00000000, 0x00112222},
|
||||
{2, DDR667 + DDR800, V1_5, NP, DIMM_DR, NP, 0, 0x003B0000, 0x00112222},
|
||||
{2, DDR667, V1_5, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, 0, 0x00390039, 0x10222322},
|
||||
{2, DDR800, V1_5, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, 0, 0x00390039, 0x20222322},
|
||||
{2, DDR1066, V1_5, NP, DIMM_SR, NP, 0, 0x00000000, 0x10112222},
|
||||
{2, DDR1066, V1_5, NP, DIMM_DR, NP, 0, 0x00380000, 0x10112222},
|
||||
{2, DDR1066, V1_5, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, 0, 0x00350037, 0x30222322},
|
||||
{2, DDR1333, V1_5, NP, DIMM_SR, NP, 0, 0x00000000, 0x20112222},
|
||||
{2, DDR1333, V1_5, NP, DIMM_DR, NP, 0, 0x00360000, 0x20112222},
|
||||
{2, DDR1333, V1_5, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, 1, 0x00000035, 0x30222322},
|
||||
{2, DDR1600, V1_5, NP, DIMM_SR, NP, 0, 0x00000000, 0x30112222},
|
||||
{2, DDR1600, V1_5, NP, DIMM_DR, NP, 1, 0x00000000, 0x30112222},
|
||||
{2, DDR1600, V1_5, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, 1, 0x00000033, 0x30222322}
|
||||
};
|
||||
CONST PSC_TBL_ENTRY SAOTblEntSOAM3 = {
|
||||
{PSCFG_SAO, SODIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_AM3, DDR3_TECHNOLOGY},
|
||||
sizeof (OrAM3SODdr3SAO) / sizeof (PSCFG_SAO_ENTRY),
|
||||
(VOID *)&OrAM3SODdr3SAO
|
||||
};
|
||||
// training configuratrions
|
||||
// Format :
|
||||
// DimmPerCh, DDRrate, VDDIO, Dimm0, Dimm1, Dimm2, 2D
|
||||
//
|
||||
STATIC CONST PSCFG_S___ENTRY OrAM3SODdr3S__[] = {
|
||||
{1, DDR667, VOLT_ALL, DIMM_SR + DIMM_DR, NP, NP, 0},
|
||||
};
|
||||
CONST PSC_TBL_ENTRY S__TblEntSOAM3 = {
|
||||
{PSCFG_S__, SODIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_AM3, DDR3_TECHNOLOGY},
|
||||
sizeof (OrAM3SODdr3S__) / sizeof (PSCFG_S___ENTRY),
|
||||
(VOID *)&OrAM3SODdr3S__
|
||||
};
|
||||
// ODT pattern for 1 DPC
|
||||
// Format:
|
||||
// Dimm0, RdODTCSHigh, RdODTCSLow, WrODTCSHigh, WrODTCSLow
|
||||
//
|
||||
STATIC CONST PSCFG_1D_ODTPAT_ENTRY Or1SODdr3OdtPat[] = {
|
||||
{DIMM_SR, 0x00000000, 0x00000000, 0x00000000, 0x00000001},
|
||||
{DIMM_DR, 0x00000000, 0x00000000, 0x00000000, 0x00000401}
|
||||
};
|
||||
CONST PSC_TBL_ENTRY OdtPat1DTblEntSOAM3 = {
|
||||
{PSCFG_ODT_PAT_1D, SODIMM_TYPE, _1DIMM, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_AM3, DDR3_TECHNOLOGY},
|
||||
sizeof (Or1SODdr3OdtPat) / sizeof (PSCFG_1D_ODTPAT_ENTRY),
|
||||
(VOID *)&Or1SODdr3OdtPat
|
||||
};
|
||||
|
||||
// ODT pattern for 2 DPC
|
||||
// Format:
|
||||
// Dimm0, Dimm1, ,RdODTCSHigh, RdODTCSLow, WrODTCSHigh, WrODTCSLow
|
||||
//
|
||||
STATIC CONST PSCFG____ODTPAT_ENTRY Or2SODdr3OdtPat[] = {
|
||||
{NP, DIMM_SR, 0x00000000, 0x00000000, 0x00000000, 0x00020000},
|
||||
{NP, DIMM_DR, 0x00000000, 0x00000000, 0x00000000, 0x08020000},
|
||||
{DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, 0x00000000, 0x01010202, 0x00000000, 0x09030603}
|
||||
};
|
||||
CONST PSC_TBL_ENTRY OdtPat2DTblEntSOAM3 = {
|
||||
{PSCFG_ODT_PAT___, SODIMM_TYPE, _2DIMM, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_AM3, DDR3_TECHNOLOGY},
|
||||
sizeof (Or2SODdr3OdtPat) / sizeof (PSCFG____ODTPAT_ENTRY),
|
||||
(VOID *)&Or2SODdr3OdtPat
|
||||
};
|
||||
|
||||
// ODT pattern for 3 DPC
|
||||
// Format:
|
||||
// Dimm0, Dimm1, Dimm2, RdODTCSHigh, RdODTCSLow, WrODTCSHigh, WrODTCSLow
|
||||
//
|
||||
STATIC CONST PSCFG_3D_ODTPAT_ENTRY Or3SODdr3OdtPat[] = {
|
||||
{NP, NP, DIMM_SR + DIMM_DR, 0x00000000, 0x00000000, 0x00000404, 0x00000000},
|
||||
{DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, 0x00000101, 0x00000404, 0x00000105, 0x00000405}
|
||||
};
|
||||
CONST PSC_TBL_ENTRY OdtPat3DTblEntSOAM3 = {
|
||||
{PSCFG_ODT_PAT_3D, SODIMM_TYPE, _3DIMM, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_AM3, DDR3_TECHNOLOGY},
|
||||
sizeof (Or3SODdr3OdtPat) / sizeof (PSCFG_3D_ODTPAT_ENTRY),
|
||||
(VOID *)&Or3SODdr3OdtPat
|
||||
};
|
||||
|
||||
// Dram Term and Dynamic Dram Term
|
||||
// Format :
|
||||
// DimmPerCh, DDRrate, VDDIO, Dimm0, Dimm1, Dimm2, Dimm, Rank, RttNom, RttWr
|
||||
//
|
||||
STATIC CONST PSCFG_RTT_ENTRY DramTermOrAM3SODIMM[] = {
|
||||
{1, DDR667 + DDR800 + DDR1066, V1_5, DIMM_SR, NP, NP, DIMM_SR, R0, 2, 0},
|
||||
{1, DDR667 + DDR800 + DDR1066, V1_5, DIMM_DR, NP, NP, DIMM_DR, R0 + R1, 2, 0},
|
||||
{1, DDR1333, V1_5, DIMM_SR, NP, NP, DIMM_SR, R0, 1, 0},
|
||||
{1, DDR1333, V1_5, DIMM_DR, NP, NP, DIMM_DR, R0 + R1, 1, 0},
|
||||
{1, DDR1600 + DDR1866, V1_5, DIMM_SR, NP, NP, DIMM_SR, R0, 3, 0},
|
||||
{1, DDR1600 + DDR1866, V1_5, DIMM_DR, NP, NP, DIMM_DR, R0 + R1, 3, 0},
|
||||
{2, DDR667 + DDR800 + DDR1066, V1_5, NP, DIMM_SR, NP, DIMM_SR, R0, 2, 0},
|
||||
{2, DDR667 + DDR800 + DDR1066, V1_5, NP, DIMM_DR, NP, DIMM_DR, R0 + R1, 2, 0},
|
||||
{2, DDR667 + DDR800 + DDR1066, V1_5, DIMM_SR, DIMM_SR + DIMM_DR, NP, DIMM_SR, R0, 3, 2},
|
||||
{2, DDR667 + DDR800 + DDR1066, V1_5, DIMM_SR, DIMM_DR, NP, DIMM_DR, R0 + R1, 3, 2},
|
||||
{2, DDR667 + DDR800 + DDR1066, V1_5, DIMM_DR, DIMM_SR, NP, DIMM_SR, R0, 3, 2},
|
||||
{2, DDR667 + DDR800 + DDR1066, V1_5, DIMM_DR, DIMM_SR + DIMM_DR, NP, DIMM_DR, R0 + R1, 3, 2},
|
||||
{2, DDR1333, V1_5, NP, DIMM_SR, NP, DIMM_SR, R0, 1, 0},
|
||||
{2, DDR1333, V1_5, NP, DIMM_DR, NP, DIMM_DR, R0 + R1, 1, 0},
|
||||
{2, DDR1333, V1_5, DIMM_SR, DIMM_SR + DIMM_DR, NP, DIMM_SR, R0, 5, 2},
|
||||
{2, DDR1333, V1_5, DIMM_SR, DIMM_DR, NP, DIMM_DR, R0 + R1, 5, 2},
|
||||
{2, DDR1333, V1_5, DIMM_DR, DIMM_SR, NP, DIMM_SR, R0, 5, 2},
|
||||
{2, DDR1333, V1_5, DIMM_DR, DIMM_SR + DIMM_DR, NP, DIMM_DR, R0 + R1, 5, 2},
|
||||
{2, DDR1600, V1_5, NP, DIMM_SR, NP, DIMM_SR, R0, 3, 2},
|
||||
{2, DDR1600, V1_5, NP, DIMM_SR, NP, DIMM_SR, R0, 3, 2},
|
||||
{2, DDR1600, V1_5, DIMM_SR, DIMM_SR, NP, DIMM_SR, R0, 4, 1}
|
||||
};
|
||||
CONST PSC_TBL_ENTRY DramTermTblEntSOAM3 = {
|
||||
{PSCFG_RTT, SODIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_AM3, DDR3_TECHNOLOGY},
|
||||
sizeof (DramTermOrAM3SODIMM) / sizeof (PSCFG_RTT_ENTRY),
|
||||
(VOID *)&DramTermOrAM3SODIMM
|
||||
};
|
||||
|
||||
// Max Freq.
|
||||
// Format :
|
||||
// DimmPerCh, Dimms, SR, DR, QR, Speed1_5V, Speed1_35V, Speed1_25V
|
||||
//
|
||||
STATIC CONST PSCFG_MAXFREQ_ENTRY ROMDATA MaxFreqOrAM3SODIMM[] = {
|
||||
{1, 1, 1, 0, 0, DDR1866_FREQUENCY, 0, 0},
|
||||
{1, 1, 0, 1, 0, DDR1866_FREQUENCY, 0, 0},
|
||||
{2, 1, 1, 0, 0, DDR1600_FREQUENCY, 0, 0},
|
||||
{2, 1, 0, 1, 0, DDR1600_FREQUENCY, 0, 0},
|
||||
{2, 2, 2, 0, 0, DDR1600_FREQUENCY, 0, 0},
|
||||
{2, 2, 1, 1, 0, DDR1333_FREQUENCY, 0, 0},
|
||||
{2, 2, 0, 2, 0, DDR1333_FREQUENCY, 0, 0}
|
||||
};
|
||||
CONST PSC_TBL_ENTRY MaxFreqTblEntSOAM3 = {
|
||||
{PSCFG_MAXFREQ, SODIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_AM3, DDR3_TECHNOLOGY},
|
||||
sizeof (MaxFreqOrAM3SODIMM) / sizeof (PSCFG_MAXFREQ_ENTRY),
|
||||
(VOID *)&MaxFreqOrAM3SODIMM
|
||||
};
|
||||
|
||||
|
|
@ -1,278 +0,0 @@
|
|||
/* $NoKeywords:$ */
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* mpUorA3.c
|
||||
*
|
||||
* Platform specific settings for OR AM3 DDR3 U-DIMM system
|
||||
*
|
||||
* @xrefitem bom "File Content Label" "Release Content"
|
||||
* @e project: AGESA
|
||||
* @e sub-project: (Mem/Ps/OR/AM3)
|
||||
* @e \$Revision: 55134 $ @e \$Date: 2011-06-16 15:27:02 -0600 (Thu, 16 Jun 2011) $
|
||||
*
|
||||
**/
|
||||
/*****************************************************************************
|
||||
*
|
||||
* Copyright (C) 2012 Advanced Micro Devices, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* ***************************************************************************
|
||||
*
|
||||
*/
|
||||
|
||||
#include "AGESA.h"
|
||||
#include "AdvancedApi.h"
|
||||
#include "PlatformMemoryConfiguration.h"
|
||||
#include "ma.h"
|
||||
#include "Ids.h"
|
||||
#include "cpuFamRegisters.h"
|
||||
#include "cpuRegisters.h"
|
||||
#include "mm.h"
|
||||
#include "mn.h"
|
||||
#include "mp.h"
|
||||
#include "Filecode.h"
|
||||
CODE_GROUP (G2_PEI)
|
||||
RDATA_GROUP (G2_PEI)
|
||||
|
||||
#define FILECODE PROC_MEM_PS_OR_AM3_MPUORA3_FILECODE
|
||||
/*----------------------------------------------------------------------------
|
||||
* DEFINITIONS AND MACROS
|
||||
*
|
||||
*----------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
* TYPEDEFS AND STRUCTURES
|
||||
*
|
||||
*----------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
* PROTOTYPES OF LOCAL FUNCTIONS
|
||||
*
|
||||
*----------------------------------------------------------------------------
|
||||
*/
|
||||
/*
|
||||
*-----------------------------------------------------------------------------
|
||||
* EXPORTED FUNCTIONS
|
||||
*
|
||||
*-----------------------------------------------------------------------------
|
||||
*/
|
||||
// Slow mode, Address timing and Output drive compensation
|
||||
// Format :
|
||||
// DimmPerCh, DDRrate, VDDIO, Dimm0, Dimm1, Dimm2, SlowMode, AddTmgCtl, ODC
|
||||
//
|
||||
STATIC CONST PSCFG_SAO_ENTRY OrAM3UDdr3SAO[] = {
|
||||
{1, DDR667 + DDR800, V1_5, DIMM_SR, NP, NP, 0, 0x00000000, 0x00112222},
|
||||
{1, DDR667 + DDR800, V1_5, DIMM_DR, NP, NP, 0, 0x003B0000, 0x00112222},
|
||||
{1, DDR1066, V1_5, DIMM_SR, NP, NP, 0, 0x00000000, 0x10112222},
|
||||
{1, DDR1066, V1_5, DIMM_DR, NP, NP, 0, 0x00380000, 0x10112222},
|
||||
{1, DDR1333, V1_5, DIMM_SR, NP, NP, 0, 0x00000000, 0x20112222},
|
||||
{1, DDR1333, V1_5, DIMM_DR, NP, NP, 0, 0x00360000, 0x20112222},
|
||||
{1, DDR1600, V1_5, DIMM_SR, NP, NP, 0, 0x00000000, 0x30112222},
|
||||
{1, DDR1600, V1_5, DIMM_DR, NP, NP, 1, 0x00000000, 0x30112222},
|
||||
{1, DDR1866, V1_5, DIMM_SR, NP, NP, 0, 0x00000000, 0x30332222},
|
||||
{1, DDR1866, V1_5, DIMM_DR, NP, NP, 1, 0x00000000, 0x30332222},
|
||||
{2, DDR667 + DDR800, V1_5, NP, DIMM_SR, NP, 0, 0x00000000, 0x00112222},
|
||||
{2, DDR667 + DDR800, V1_5, NP, DIMM_DR, NP, 0, 0x003B0000, 0x00112222},
|
||||
{2, DDR667, V1_5, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, 0, 0x00390039, 0x10222322},
|
||||
{2, DDR800, V1_5, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, 0, 0x00390039, 0x20222322},
|
||||
{2, DDR1066, V1_5, NP, DIMM_SR, NP, 0, 0x00000000, 0x10112222},
|
||||
{2, DDR1066, V1_5, NP, DIMM_DR, NP, 0, 0x00380000, 0x10112222},
|
||||
{2, DDR1066, V1_5, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, 0, 0x00350037, 0x30222322},
|
||||
{2, DDR1333, V1_5, NP, DIMM_SR, NP, 0, 0x00000000, 0x20112222},
|
||||
{2, DDR1333, V1_5, NP, DIMM_DR, NP, 0, 0x00360000, 0x20112222},
|
||||
{2, DDR1333, V1_5, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, 1, 0x00000035, 0x30222322},
|
||||
{2, DDR1600, V1_5, NP, DIMM_SR, NP, 0, 0x00000000, 0x30112222},
|
||||
{2, DDR1600, V1_5, NP, DIMM_DR, NP, 1, 0x00000000, 0x30112222},
|
||||
{2, DDR1600, V1_5, DIMM_SR, DIMM_SR, NP, 1, 0x00000033, 0x30222322},
|
||||
{2, DDR1600, V1_5, DIMM_SR, DIMM_DR, NP, 1, 0x00000033, 0x30222322},
|
||||
{2, DDR1600, V1_5, DIMM_DR, DIMM_SR + DIMM_DR, NP, 1, 0x00000033, 0x30222322},
|
||||
{2, DDR1866, V1_5, NP, DIMM_SR, NP, 0, 0x00000000, 0x30332222},
|
||||
{2, DDR1866, V1_5, NP, DIMM_DR, NP, 1, 0x00000000, 0x30332222},
|
||||
};
|
||||
CONST PSC_TBL_ENTRY SAOTblEntUAM3 = {
|
||||
{PSCFG_SAO, UDIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_AM3, DDR3_TECHNOLOGY},
|
||||
sizeof (OrAM3UDdr3SAO) / sizeof (PSCFG_SAO_ENTRY),
|
||||
(VOID *)&OrAM3UDdr3SAO
|
||||
};
|
||||
// training configuratrions
|
||||
// Format :
|
||||
// DimmPerCh, DDRrate, VDDIO, Dimm0, Dimm1, Dimm2, 2D
|
||||
//
|
||||
STATIC CONST PSCFG_S___ENTRY OrAM3UDdr3S__[] = {
|
||||
// DimmPerCh,Frequency,VDDIO,DIMM0,DIMM1,DIMM2,Enable__Training
|
||||
{1, DDR667 + DDR800 + DDR1066 + DDR1333 + DDR1600 + DDR1866, V1_5, DIMM_SR + DIMM_DR, NP, NP, 0},
|
||||
// DimmPerCh,Frequency,VDDIO,DIMM0,DIMM1,DIMM2,Enable__Training
|
||||
{2, DDR667 + DDR800 + DDR1066 + DDR1333, V1_5, NP + DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, 0},
|
||||
{2, DDR1600, V1_5, NP, DIMM_SR + DIMM_DR, NP, 0},
|
||||
{2, DDR1600, V1_5, DIMM_SR, DIMM_SR, NP, 0},
|
||||
{2, DDR1600, V1_5, DIMM_SR, DIMM_DR, NP, 0},
|
||||
{2, DDR1600, V1_5, DIMM_DR, DIMM_SR + DIMM_DR, NP, 0},
|
||||
{2, DDR1866, V1_5, NP, DIMM_SR + DIMM_DR, NP, 0}, };
|
||||
CONST PSC_TBL_ENTRY S__TblEntUAM3 = {
|
||||
{PSCFG_S__, UDIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_AM3, DDR3_TECHNOLOGY},
|
||||
sizeof (OrAM3UDdr3S__) / sizeof (PSCFG_S___ENTRY),
|
||||
(VOID *)&OrAM3UDdr3S__
|
||||
};
|
||||
// ODT pattern for 1 DPC
|
||||
// Format:
|
||||
// Dimm0, RdODTCSHigh, RdODTCSLow, WrODTCSHigh, WrODTCSLow
|
||||
//
|
||||
STATIC CONST PSCFG_1D_ODTPAT_ENTRY Or1UDdr3OdtPat[] = {
|
||||
{DIMM_SR, 0x00000000, 0x00000000, 0x00000000, 0x00000001},
|
||||
{DIMM_DR, 0x00000000, 0x00000000, 0x00000000, 0x00000401}
|
||||
};
|
||||
CONST PSC_TBL_ENTRY OdtPat1DTblEntUAM3 = {
|
||||
{PSCFG_ODT_PAT_1D, UDIMM_TYPE, _1DIMM, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_AM3, DDR3_TECHNOLOGY},
|
||||
sizeof (Or1UDdr3OdtPat) / sizeof (PSCFG_1D_ODTPAT_ENTRY),
|
||||
(VOID *)&Or1UDdr3OdtPat
|
||||
};
|
||||
|
||||
// ODT pattern for 2 DPC
|
||||
// Format:
|
||||
// Dimm0, Dimm1, ,RdODTCSHigh, RdODTCSLow, WrODTCSHigh, WrODTCSLow
|
||||
//
|
||||
STATIC CONST PSCFG____ODTPAT_ENTRY Or2UDdr3OdtPat[] = {
|
||||
{NP, DIMM_SR, 0x00000000, 0x00000000, 0x00000000, 0x00020000},
|
||||
{NP, DIMM_DR, 0x00000000, 0x00000000, 0x00000000, 0x08020000},
|
||||
{DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, 0x00000000, 0x01010202, 0x00000000, 0x09030603}
|
||||
};
|
||||
CONST PSC_TBL_ENTRY OdtPat2DTblEntUAM3 = {
|
||||
{PSCFG_ODT_PAT___, UDIMM_TYPE, _2DIMM, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_AM3, DDR3_TECHNOLOGY},
|
||||
sizeof (Or2UDdr3OdtPat) / sizeof (PSCFG____ODTPAT_ENTRY),
|
||||
(VOID *)&Or2UDdr3OdtPat
|
||||
};
|
||||
|
||||
// ODT pattern for 3 DPC
|
||||
// Format:
|
||||
// Dimm0, Dimm1, Dimm2, RdODTCSHigh, RdODTCSLow, WrODTCSHigh, WrODTCSLow
|
||||
//
|
||||
STATIC CONST PSCFG_3D_ODTPAT_ENTRY Or3UDdr3OdtPat[] = {
|
||||
{NP, NP, DIMM_SR + DIMM_DR, 0x00000000, 0x00000000, 0x00000004, 0x00000000},
|
||||
{DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, 0x00000101, 0x00000404, 0x00000105, 0x00000405}
|
||||
};
|
||||
CONST PSC_TBL_ENTRY OdtPat3DTblEntUAM3 = {
|
||||
{PSCFG_ODT_PAT_3D, UDIMM_TYPE, _3DIMM, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_AM3, DDR3_TECHNOLOGY},
|
||||
sizeof (Or3UDdr3OdtPat) / sizeof (PSCFG_3D_ODTPAT_ENTRY),
|
||||
(VOID *)&Or3UDdr3OdtPat
|
||||
};
|
||||
|
||||
// Dram Term and Dynamic Dram Term
|
||||
// Format :
|
||||
// DimmPerCh, DDRrate, VDDIO, Dimm0, Dimm1, Dimm2, Dimm, Rank, RttNom, RttWr
|
||||
//
|
||||
STATIC CONST PSCFG_RTT_ENTRY DramTermOrAM3UDIMM[] = {
|
||||
{1, DDR667 + DDR800 + DDR1066, V1_5, DIMM_SR, NP, NP, DIMM_SR, R0, 2, 0},
|
||||
{1, DDR667 + DDR800 + DDR1066, V1_5, DIMM_DR, NP, NP, DIMM_DR, R0 + R1, 2, 0},
|
||||
{1, DDR1333, V1_5, DIMM_SR, NP, NP, DIMM_SR, R0, 1, 0},
|
||||
{1, DDR1333, V1_5, DIMM_DR, NP, NP, DIMM_DR, R0 + R1, 1, 0},
|
||||
{1, DDR1600 + DDR1866, V1_5, DIMM_SR, NP, NP, DIMM_SR, R0, 3, 0},
|
||||
{1, DDR1600 + DDR1866, V1_5, DIMM_DR, NP, NP, DIMM_DR, R0 + R1, 3, 0},
|
||||
{2, DDR667 + DDR800 + DDR1066, V1_5, NP, DIMM_SR, NP, DIMM_SR, R0, 2, 0},
|
||||
{2, DDR667 + DDR800 + DDR1066, V1_5, NP, DIMM_DR, NP, DIMM_DR, R0 + R1, 2, 0},
|
||||
{2, DDR667 + DDR800 + DDR1066, V1_5, DIMM_SR, DIMM_SR + DIMM_DR, NP, DIMM_SR, R0, 3, 2},
|
||||
{2, DDR667 + DDR800 + DDR1066, V1_5, DIMM_SR, DIMM_DR, NP, DIMM_DR, R0 + R1, 3, 2},
|
||||
{2, DDR667 + DDR800 + DDR1066, V1_5, DIMM_DR, DIMM_SR, NP, DIMM_SR, R0, 3, 2},
|
||||
{2, DDR667 + DDR800 + DDR1066, V1_5, DIMM_DR, DIMM_SR + DIMM_DR, NP, DIMM_DR, R0 + R1, 3, 2},
|
||||
{2, DDR1333, V1_5, NP, DIMM_SR, NP, DIMM_SR, R0, 1, 0},
|
||||
{2, DDR1333, V1_5, NP, DIMM_DR, NP, DIMM_DR, R0 + R1, 1, 0},
|
||||
{2, DDR1333, V1_5, DIMM_SR, DIMM_SR + DIMM_DR, NP, DIMM_SR, R0, 5, 2},
|
||||
{2, DDR1333, V1_5, DIMM_SR, DIMM_DR, NP, DIMM_DR, R0 + R1, 5, 2},
|
||||
{2, DDR1333, V1_5, DIMM_DR, DIMM_SR, NP, DIMM_SR, R0, 5, 2},
|
||||
{2, DDR1333, V1_5, DIMM_DR, DIMM_SR + DIMM_DR, NP, DIMM_DR, R0 + R1, 5, 2},
|
||||
{2, DDR1600, V1_5, NP, DIMM_SR, NP, DIMM_SR, R0, 3, 0},
|
||||
{2, DDR1600, V1_5, NP, DIMM_DR, NP, DIMM_DR, R0 + R1, 3, 0},
|
||||
{2, DDR1600, V1_5, DIMM_SR, DIMM_SR, NP, DIMM_SR, R0, 4, 1},
|
||||
{2, DDR1600, V1_5, DIMM_SR, DIMM_DR, NP, DIMM_SR, R0, 4, 1},
|
||||
{2, DDR1600, V1_5, DIMM_SR, DIMM_DR, NP, DIMM_DR, R0 + R1, 4, 1},
|
||||
{2, DDR1600, V1_5, DIMM_DR, DIMM_SR, NP, DIMM_SR, R0, 4, 1},
|
||||
{2, DDR1600, V1_5, DIMM_DR, DIMM_SR + DIMM_DR, NP, DIMM_DR, R0 + R1, 4, 1},
|
||||
{2, DDR1866, V1_5, NP, DIMM_SR, NP, DIMM_SR, R0, 3, 0},
|
||||
{2, DDR1866, V1_5, NP, DIMM_DR, NP, DIMM_DR, R0 + R1, 3, 0},
|
||||
};
|
||||
CONST PSC_TBL_ENTRY DramTermTblEntUAM3 = {
|
||||
{PSCFG_RTT, UDIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_AM3, DDR3_TECHNOLOGY},
|
||||
sizeof (DramTermOrAM3UDIMM) / sizeof (PSCFG_RTT_ENTRY),
|
||||
(VOID *)&DramTermOrAM3UDIMM
|
||||
};
|
||||
|
||||
// Max Freq.
|
||||
// Format :
|
||||
// DimmPerCh, Dimms, SR, DR, QR, Speed1_5V, Speed1_35V, Speed1_25V
|
||||
//
|
||||
STATIC CONST PSCFG_MAXFREQ_ENTRY ROMDATA MaxFreqOrAM3UDIMM[] = {
|
||||
{1, 1, 1, 0, 0, DDR1866_FREQUENCY, 0, 0},
|
||||
{1, 1, 0, 1, 0, DDR1866_FREQUENCY, 0, 0},
|
||||
{2, 1, 1, 0, 0, DDR1600_FREQUENCY, 0, 0},
|
||||
{2, 1, 0, 1, 0, DDR1600_FREQUENCY, 0, 0},
|
||||
{2, 2, 2, 0, 0, DDR1600_FREQUENCY, 0, 0},
|
||||
{2, 2, 1, 1, 0, DDR1333_FREQUENCY, 0, 0},
|
||||
{2, 2, 0, 2, 0, DDR1333_FREQUENCY, 0, 0}
|
||||
};
|
||||
CONST PSC_TBL_ENTRY MaxFreqTblEntUAM3 = {
|
||||
{PSCFG_MAXFREQ, UDIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_AM3, DDR3_TECHNOLOGY},
|
||||
sizeof (MaxFreqOrAM3UDIMM) / sizeof (PSCFG_MAXFREQ_ENTRY),
|
||||
(VOID *)&MaxFreqOrAM3UDIMM
|
||||
};
|
||||
|
||||
//
|
||||
// MemClkDis
|
||||
//
|
||||
STATIC CONST UINT8 ROMDATA OrUDdr3CLKDis[] = {0x02, 0x01, 0x08, 0x04, 0x00, 0x00, 0x00, 0x00};
|
||||
CONST PSC_TBL_ENTRY ClkDisMapEntUAM3 = {
|
||||
{PSCFG_CLKDIS, UDIMM_TYPE, _1DIMM + _2DIMM, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_AM3, DDR3_TECHNOLOGY},
|
||||
sizeof (OrUDdr3CLKDis) / sizeof (UINT8),
|
||||
(VOID *)&OrUDdr3CLKDis
|
||||
};
|
||||
|
||||
//
|
||||
// WL pass1 seed
|
||||
//
|
||||
// Format :
|
||||
// DimmPerCh in bit map, Channel #, Seed value
|
||||
STATIC CONST PSCFG_SEED_ENTRY ROMDATA WLPas1SeedOrAM3UDIMM[] = {
|
||||
{_1DIMM + _2DIMM + _3DIMM, CH_ALL, 0x0F}
|
||||
};
|
||||
CONST PSC_TBL_ENTRY WLPass1SeedEntUAM3 = {
|
||||
{PSCFG_WL_PASS1_SEED, UDIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_AM3, DDR3_TECHNOLOGY},
|
||||
sizeof (WLPas1SeedOrAM3UDIMM) / sizeof (PSCFG_SEED_ENTRY),
|
||||
(VOID *)&WLPas1SeedOrAM3UDIMM
|
||||
};
|
||||
|
||||
//
|
||||
// HW RxEn pass1 seed
|
||||
//
|
||||
// Format :
|
||||
// DimmPerCh in bit map, Channel #, Seed value
|
||||
STATIC CONST PSCFG_SEED_ENTRY ROMDATA HWRxEnPas1SeedOrAM3UDIMM[] = {
|
||||
{_1DIMM + _2DIMM, CH_A + CH_B, 0x3A},
|
||||
};
|
||||
CONST PSC_TBL_ENTRY HWRxEnPass1SeedEntUAM3 = {
|
||||
{PSCFG_HWRXEN_PASS1_SEED, UDIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_15_OR, AMD_F15_ALL}, OR_SOCKET_AM3, DDR3_TECHNOLOGY},
|
||||
sizeof (HWRxEnPas1SeedOrAM3UDIMM) / sizeof (PSCFG_SEED_ENTRY),
|
||||
(VOID *)&HWRxEnPas1SeedOrAM3UDIMM
|
||||
};
|
||||
|
|
@ -1,233 +0,0 @@
|
|||
/* $NoKeywords:$ */
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* mt2.c
|
||||
*
|
||||
* Common Technology functions for DDR2
|
||||
*
|
||||
* @xrefitem bom "File Content Label" "Release Content"
|
||||
* @e project: AGESA
|
||||
* @e sub-project: (Mem/Tech/DDR2)
|
||||
* @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $
|
||||
*
|
||||
**/
|
||||
/*****************************************************************************
|
||||
*
|
||||
* Copyright (C) 2012 Advanced Micro Devices, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* ***************************************************************************
|
||||
*
|
||||
*/
|
||||
|
||||
/*
|
||||
*----------------------------------------------------------------------------
|
||||
* MODULES USED
|
||||
*
|
||||
*----------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#include "AGESA.h"
|
||||
#include "Ids.h"
|
||||
#include "AdvancedApi.h"
|
||||
#include "mm.h"
|
||||
#include "mn.h"
|
||||
#include "mu.h"
|
||||
#include "mt.h"
|
||||
#include "mt2.h"
|
||||
#include "mtspd2.h"
|
||||
#include "mtot2.h"
|
||||
#include "OptionMemory.h"
|
||||
#include "PlatformMemoryConfiguration.h"
|
||||
#include "Filecode.h"
|
||||
CODE_GROUP (G1_PEICC)
|
||||
RDATA_GROUP (G2_PEI)
|
||||
|
||||
/* features */
|
||||
#include "mftds.h"
|
||||
#define FILECODE PROC_MEM_TECH_DDR2_MT2_FILECODE
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
* DEFINITIONS AND MACROS
|
||||
*
|
||||
*----------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
* TYPEDEFS AND STRUCTURES
|
||||
*
|
||||
*----------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
* PROTOTYPES OF LOCAL FUNCTIONS
|
||||
*
|
||||
*----------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
* EXPORTED FUNCTIONS
|
||||
*
|
||||
*----------------------------------------------------------------------------
|
||||
*/
|
||||
/* -----------------------------------------------------------------------------*/
|
||||
/**
|
||||
*
|
||||
* This function Constructs the technology block
|
||||
*
|
||||
* @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
|
||||
* @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
|
||||
*
|
||||
*/
|
||||
|
||||
BOOLEAN
|
||||
MemConstructTechBlock2 (
|
||||
IN OUT MEM_TECH_BLOCK *TechPtr,
|
||||
IN OUT MEM_NB_BLOCK *NBPtr
|
||||
)
|
||||
{
|
||||
TECHNOLOGY_TYPE *TechTypePtr;
|
||||
UINT8 Dct;
|
||||
UINT8 Channel;
|
||||
UINT8 i;
|
||||
DIE_STRUCT *MCTPtr;
|
||||
DCT_STRUCT *DCTPtr;
|
||||
CH_DEF_STRUCT *ChannelPtr;
|
||||
UINT8 DimmSlots;
|
||||
|
||||
TechTypePtr = (TECHNOLOGY_TYPE *) FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_MEM_TECH, NBPtr->MCTPtr->SocketId, 0, 0, NULL, NULL);
|
||||
if (TechTypePtr != NULL) {
|
||||
// Ensure the platform override value is valid
|
||||
ASSERT ((*TechTypePtr == DDR3_TECHNOLOGY) || (*TechTypePtr == DDR2_TECHNOLOGY));
|
||||
if (*TechTypePtr != DDR2_TECHNOLOGY) {
|
||||
return FALSE;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
TechPtr->NBPtr = NBPtr;
|
||||
TechPtr->RefPtr = NBPtr->RefPtr;
|
||||
MCTPtr = NBPtr->MCTPtr;
|
||||
|
||||
TechPtr->NBPtr = NBPtr;
|
||||
TechPtr->RefPtr = NBPtr->RefPtr;
|
||||
|
||||
TechPtr->SetDramMode = MemTSetDramMode2;
|
||||
TechPtr->DimmPresence = MemTDIMMPresence2;
|
||||
TechPtr->SpdCalcWidth = MemTSPDCalcWidth2;
|
||||
TechPtr->SpdGetTargetSpeed = MemTSPDGetTargetSpeed2;
|
||||
TechPtr->AutoCycTiming = MemTAutoCycTiming2;
|
||||
TechPtr->SpdSetBanks = MemTSPDSetBanks2;
|
||||
TechPtr->SetDqsEccTmgs = MemTSetDQSEccTmgs;
|
||||
TechPtr->GetCSIntLvAddr = MemTGetCSIntLvAddr2;
|
||||
TechPtr->AdjustTwrwr = MemTAdjustTwrwr2;
|
||||
TechPtr->AdjustTwrrd = MemTAdjustTwrrd2;
|
||||
TechPtr->GetDimmSpdBuffer = MemTGetDimmSpdBuffer2;
|
||||
TechPtr->GetLD = MemTGetLD2;
|
||||
TechPtr->MaxFilterDly = 0;
|
||||
|
||||
//
|
||||
// Map the Logical Dimms on this channel to the SPD that should be used for that logical DIMM.
|
||||
// The pointers to the DIMM SPD information is as follows (2 Dimm/Ch and 3 Dimm/Ch examples).
|
||||
//
|
||||
// DIMM Spd Buffer Current Channel DimmSpdPtr[MAX_DIMMS_PER_CHANNEL] array
|
||||
// (Number of dimms varies by platform) (Array size is determined in AGESA.H) Dimm operations loop
|
||||
// on this array only)
|
||||
// 2 DIMMS PER CHANNEL
|
||||
//
|
||||
// Socket N Channel N Dimm 0 SR/DR DIMM <--------------DimmSpdPtr[0]
|
||||
// Dimm 1 SR/DR DIMM <--------------DimmSpdPtr[1]
|
||||
// DimmSpdPtr[2]------->NULL
|
||||
// DimmSpdPtr[3]------->NULL
|
||||
//
|
||||
// Socket N Channel N Dimm 0 SR/DR DIMM <--------------DimmSpdPtr[0]
|
||||
// Dimm 1 QR DIMM <---------+----DimmSpdPtr[1]
|
||||
// | DimmSpdPtr[2]------->NULL
|
||||
// +----DimmSpdPtr[3]
|
||||
//
|
||||
// Socket N Channel N Dimm 0 QR DIMM <-----+--------DimmSpdPtr[0]
|
||||
// Dimm 1 QR DIMM <-----|---+----DimmSpdPtr[1]
|
||||
// +-- | ---DimmSpdPtr[2]
|
||||
// +----DimmSpdPtr[3]
|
||||
//
|
||||
// 3 DIMMS PER CHANNEL
|
||||
//
|
||||
// Socket N Channel N Dimm 0 SR/DR DIMM <--------------DimmSpdPtr[0]
|
||||
// Dimm 1 SR/DR DIMM <--------------DimmSpdPtr[1]
|
||||
// Dimm 3 SR/DR DIMM <--------------DimmSpdPtr[2]
|
||||
// DimmSpdPtr[3]------->NULL
|
||||
//
|
||||
// Socket N Channel N Dimm 0 SR/DR DIMM <--------------DimmSpdPtr[0]
|
||||
// Dimm 1 QR DIMM <---------+----DimmSpdPtr[1]
|
||||
// Dimm 3 SR/DR DIMM <-------- | ---DimmSpdPtr[2]
|
||||
// +----DimmSpdPtr[3]
|
||||
//
|
||||
//
|
||||
|
||||
for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
|
||||
NBPtr->SwitchDCT (NBPtr, Dct);
|
||||
DCTPtr = NBPtr->DCTPtr;
|
||||
for (Channel = 0; Channel < NBPtr->ChannelCount; Channel++) {
|
||||
NBPtr->SwitchChannel (NBPtr, Channel);
|
||||
ChannelPtr = NBPtr->ChannelPtr;
|
||||
ChannelPtr->TechType = DDR2_TECHNOLOGY;
|
||||
ChannelPtr->MCTPtr = MCTPtr;
|
||||
ChannelPtr->DCTPtr = DCTPtr;
|
||||
|
||||
DimmSlots = GetMaxDimmsPerChannel (NBPtr->RefPtr->PlatformMemoryConfiguration,
|
||||
MCTPtr->SocketId,
|
||||
NBPtr->GetSocketRelativeChannel (NBPtr, Dct, Channel)
|
||||
);
|
||||
//
|
||||
// Initialize the SPD pointers for each Dimm
|
||||
//
|
||||
for (i = 0 ; i < (sizeof (ChannelPtr->DimmSpdPtr) / sizeof (ChannelPtr->DimmSpdPtr[0])) ; i++) {
|
||||
ChannelPtr->DimmSpdPtr[i] = NULL;
|
||||
}
|
||||
for (i = 0 ; i < DimmSlots; i++) {
|
||||
ChannelPtr->DimmSpdPtr[i] = &(ChannelPtr->SpdPtr[i]);
|
||||
if ( (i + 2) < (sizeof (ChannelPtr->DimmSpdPtr) / sizeof (ChannelPtr->DimmSpdPtr[0]))) {
|
||||
if (ChannelPtr->DimmSpdPtr[i]->DimmPresent) {
|
||||
if ((((ChannelPtr->DimmSpdPtr[i]->Data[SPD_DM_BANKS] >> 3) & 0x07) + 1) > 2) {
|
||||
ChannelPtr->DimmSpdPtr[i + 2] = &(ChannelPtr->SpdPtr[i]);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
* LOCAL FUNCTIONS
|
||||
*
|
||||
*----------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
|
||||
|
|
@ -1,125 +0,0 @@
|
|||
/* $NoKeywords:$ */
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* mt2.h
|
||||
*
|
||||
* Common Technology
|
||||
*
|
||||
* @xrefitem bom "File Content Label" "Release Content"
|
||||
* @e project: AGESA
|
||||
* @e sub-project: (Mem/Tech/DDR2)
|
||||
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $
|
||||
*
|
||||
**/
|
||||
/*****************************************************************************
|
||||
*
|
||||
* Copyright (C) 2012 Advanced Micro Devices, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* ***************************************************************************
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _MT2_H_
|
||||
#define _MT2_H_
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
* Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
|
||||
*
|
||||
*----------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
* DEFINITIONS AND MACROS
|
||||
*
|
||||
*-----------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
* TYPEDEFS, STRUCTURES, ENUMS
|
||||
*
|
||||
*----------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
* FUNCTIONS PROTOTYPE
|
||||
*
|
||||
*----------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
BOOLEAN
|
||||
MemConstructTechBlock2 (
|
||||
IN OUT MEM_TECH_BLOCK *TechPtr,
|
||||
IN OUT MEM_NB_BLOCK *NBPtr
|
||||
);
|
||||
|
||||
BOOLEAN
|
||||
MemTSetDramMode2 (
|
||||
IN OUT MEM_TECH_BLOCK *TechPtr
|
||||
);
|
||||
|
||||
BOOLEAN
|
||||
MemTDIMMPresence2 (
|
||||
IN OUT MEM_TECH_BLOCK *TechPtr
|
||||
);
|
||||
|
||||
BOOLEAN
|
||||
MemTSPDCalcWidth2 (
|
||||
IN OUT MEM_TECH_BLOCK *TechPtr
|
||||
);
|
||||
|
||||
BOOLEAN
|
||||
MemTSPDGetTargetSpeed2 (
|
||||
IN OUT MEM_TECH_BLOCK *TechPtr
|
||||
);
|
||||
|
||||
BOOLEAN
|
||||
MemTAutoCycTiming2 (
|
||||
IN OUT MEM_TECH_BLOCK *TechPtr
|
||||
);
|
||||
|
||||
BOOLEAN
|
||||
MemTSPDSetBanks2 (
|
||||
IN OUT MEM_TECH_BLOCK *TechPtr
|
||||
);
|
||||
|
||||
VOID
|
||||
MemTGetCSIntLvAddr2 (
|
||||
IN UINT8 BankEnc,
|
||||
OUT UINT8 *LowBit,
|
||||
OUT UINT8 *HiBit
|
||||
);
|
||||
|
||||
BOOLEAN
|
||||
MemTGetDimmSpdBuffer2 (
|
||||
IN OUT MEM_TECH_BLOCK *TechPtr,
|
||||
IN OUT UINT8 **SpdBuffer,
|
||||
IN UINT8 Dimm
|
||||
);
|
||||
|
||||
#endif /* _MT2_H_ */
|
||||
|
||||
|
||||
|
|
@ -1,163 +0,0 @@
|
|||
/* $NoKeywords:$ */
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* mtot2.c
|
||||
*
|
||||
* Technology Non-SPD Timings for DDR2
|
||||
*
|
||||
* @xrefitem bom "File Content Label" "Release Content"
|
||||
* @e project: AGESA
|
||||
* @e sub-project: (Mem/Tech/DDR2)
|
||||
* @e \$Revision: 56279 $ @e \$Date: 2011-07-11 13:11:28 -0600 (Mon, 11 Jul 2011) $
|
||||
*
|
||||
**/
|
||||
/*****************************************************************************
|
||||
*
|
||||
* Copyright (C) 2012 Advanced Micro Devices, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* ***************************************************************************
|
||||
*
|
||||
*/
|
||||
|
||||
/*
|
||||
*----------------------------------------------------------------------------
|
||||
* MODULES USED
|
||||
*
|
||||
*----------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#include "AGESA.h"
|
||||
#include "mm.h"
|
||||
#include "mn.h"
|
||||
#include "mu.h"
|
||||
#include "mt.h"
|
||||
#include "mtot2.h"
|
||||
#include "Filecode.h"
|
||||
CODE_GROUP (G1_PEICC)
|
||||
RDATA_GROUP (G2_PEI)
|
||||
|
||||
#define FILECODE PROC_MEM_TECH_DDR2_MTOT2_FILECODE
|
||||
/*----------------------------------------------------------------------------
|
||||
* DEFINITIONS AND MACROS
|
||||
*
|
||||
*----------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
* TYPEDEFS AND STRUCTURES
|
||||
*
|
||||
*----------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
* PROTOTYPES OF LOCAL FUNCTIONS
|
||||
*
|
||||
*----------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
* EXPORTED FUNCTIONS
|
||||
*
|
||||
*----------------------------------------------------------------------------
|
||||
*/
|
||||
/* -----------------------------------------------------------------------------*/
|
||||
/**
|
||||
*
|
||||
* This function adjusts the Twrwr value for DDR2.
|
||||
*
|
||||
* @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
|
||||
*
|
||||
*/
|
||||
|
||||
VOID
|
||||
MemTAdjustTwrwr2 (
|
||||
IN OUT MEM_TECH_BLOCK *TechPtr
|
||||
)
|
||||
{
|
||||
DCT_STRUCT *DCTPtr;
|
||||
|
||||
DCTPtr = TechPtr->NBPtr->DCTPtr;
|
||||
|
||||
// For DDR2, 1 clock has encoded value of 0.
|
||||
// Need to transfer clk value to encoded value.
|
||||
if (DCTPtr->Timings.Twrwr >= 1) {
|
||||
DCTPtr->Timings.Twrwr -= 1;
|
||||
}
|
||||
}
|
||||
|
||||
/* -----------------------------------------------------------------------------*/
|
||||
/**
|
||||
*
|
||||
* This function adjusts the Twrrd value for DDR2.
|
||||
*
|
||||
* @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
|
||||
*
|
||||
*/
|
||||
|
||||
VOID
|
||||
MemTAdjustTwrrd2 (
|
||||
IN OUT MEM_TECH_BLOCK *TechPtr
|
||||
)
|
||||
{
|
||||
DCT_STRUCT *DCTPtr;
|
||||
|
||||
DCTPtr = TechPtr->NBPtr->DCTPtr;
|
||||
|
||||
// For DDR2, 1 clock has encoded value of 0.
|
||||
// Need to transfer clk value to encoded value.
|
||||
if (DCTPtr->Timings.Twrrd >= 1) {
|
||||
DCTPtr->Timings.Twrrd -= 1;
|
||||
}
|
||||
}
|
||||
|
||||
/* -----------------------------------------------------------------------------*/
|
||||
/**
|
||||
*
|
||||
* This function gets the LD value for DDR2
|
||||
*
|
||||
* @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
|
||||
*
|
||||
* @return value of LD
|
||||
*/
|
||||
|
||||
INT8
|
||||
MemTGetLD2 (
|
||||
IN OUT MEM_TECH_BLOCK *TechPtr
|
||||
)
|
||||
{
|
||||
INT8 LD;
|
||||
|
||||
// For DDR2, LD is always one clock (For DDR2, Tcwl is always Tcl minus 1).
|
||||
LD = 1;
|
||||
|
||||
return LD;
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
|
@ -1,89 +0,0 @@
|
|||
/* $NoKeywords:$ */
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* mtot2.h
|
||||
*
|
||||
* Technology Non-SPD timings for DDR2
|
||||
*
|
||||
* @xrefitem bom "File Content Label" "Release Content"
|
||||
* @e project: AGESA
|
||||
* @e sub-project: (Mem/Tech/DDR2)
|
||||
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $
|
||||
*
|
||||
**/
|
||||
/*****************************************************************************
|
||||
*
|
||||
* Copyright (C) 2012 Advanced Micro Devices, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* ***************************************************************************
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _MTOT2_H_
|
||||
#define _MTOT2_H_
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
* Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
|
||||
*
|
||||
*----------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
* DEFINITIONS AND MACROS
|
||||
*
|
||||
*-----------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
* TYPEDEFS, STRUCTURES, ENUMS
|
||||
*
|
||||
*----------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
* FUNCTIONS PROTOTYPE
|
||||
*
|
||||
*----------------------------------------------------------------------------
|
||||
*/
|
||||
VOID
|
||||
MemTAdjustTwrwr2 (
|
||||
IN OUT MEM_TECH_BLOCK *TechPtr
|
||||
);
|
||||
|
||||
VOID
|
||||
MemTAdjustTwrrd2 (
|
||||
IN OUT MEM_TECH_BLOCK *TechPtr
|
||||
);
|
||||
|
||||
INT8
|
||||
MemTGetLD2 (
|
||||
IN OUT MEM_TECH_BLOCK *TechPtr
|
||||
);
|
||||
|
||||
#endif /* _MTOT2_H_ */
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,183 +0,0 @@
|
|||
/* $NoKeywords:$ */
|
||||
/**
|
||||
* @file
|
||||
*
|
||||
* mtspd2.h
|
||||
*
|
||||
* Technology SPD support for DDR2
|
||||
*
|
||||
* @xrefitem bom "File Content Label" "Release Content"
|
||||
* @e project: AGESA
|
||||
* @e sub-project: (Mem/Tech/DDR2)
|
||||
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 02:16:51 -0700 (Wed, 22 Dec 2010) $
|
||||
*
|
||||
**/
|
||||
/*****************************************************************************
|
||||
*
|
||||
* Copyright (C) 2012 Advanced Micro Devices, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
|
||||
* its contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* ***************************************************************************
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _MTSPD2_H_
|
||||
#define _MTSPD2_H_
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
* Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
|
||||
*
|
||||
*----------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
* DEFINITIONS AND MACROS
|
||||
*
|
||||
*-----------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*===============================================================================
|
||||
* Jedec DDR II
|
||||
*===============================================================================
|
||||
*/
|
||||
#define SPD_TYPE 2 /* SPD byte read location */
|
||||
#define JED_DDR_SDRAM 7 /* Jedec defined bit field */
|
||||
#define JED_DDR2_SDRAM 8 /* Jedec defined bit field */
|
||||
|
||||
#define SPD_DIMM_TYPE 20
|
||||
#define SPD_ATTRIB 21
|
||||
#define JED_DIF_CK_MSK 0x20 /* Differential Clock Input */
|
||||
#define JED_REG_ADC_MSK 0x11 /* Registered Address/Control */
|
||||
#define JED_PROBE_MSK 0x40 /* Analysis Probe installed */
|
||||
#define JED_SODIMM 0x04 /* SO-DIMM */
|
||||
#define SPD_DEV_ATTRIB 22
|
||||
#define SPD_EDC_TYPE 11
|
||||
#define JED_ECC 2
|
||||
#define JED_ADRC_PAR 4
|
||||
#define SPD_ROW_SZ 3
|
||||
#define SPD_COL_SZ 4
|
||||
#define SPD_L_BANKS 17 /* number of [logical] banks on each device */
|
||||
#define SPD_DM_BANKS 5 /* number of physical banks on dimm */
|
||||
#define SP_DPL_BIT 4 /* Dram package bit */
|
||||
#define SPD_BANK_SZ 31 /* capacity of physical bank */
|
||||
#define SPD_DEV_WIDTH 13
|
||||
#define SPD_CAS_LAT 18
|
||||
#define SPD_TRP 27
|
||||
#define SPD_TRRD 28
|
||||
#define SPD_TRCD 29
|
||||
#define SPD_TRAS 30
|
||||
#define SPD_TWR 36
|
||||
#define SPD_TWTR 37
|
||||
#define SPD_TRTP 38
|
||||
#define SPD_TRC 41
|
||||
#define SPD_TRFC 42
|
||||
#define SPD_CHECKSUM 63
|
||||
#define SPD_MAN_DATE_YR 93 /* Module Manufacturing Year (BCD) */
|
||||
|
||||
#define SPD_MAN_DATE_WK 94 /* Module Manufacturing Week (BCD) */
|
||||
|
||||
/*-----------------------------
|
||||
* Jedec DDR II related equates
|
||||
*-----------------------------
|
||||
*/
|
||||
#define M_YEAR_06 0x06 /* Manufacturing Year BCD encoding of 2006 - 06d */
|
||||
#define M_WEEK_24 0x24 /* Manufacturing Week BCD encoding of June - 24d */
|
||||
|
||||
#define J_MIN 0 /* j loop constraint. 1=CL 2.0 T */
|
||||
#define J_MAX 5 /* j loop constraint. 5=CL 7.0 T */
|
||||
#define K_MIN 1 /* k loop constraint. 1=200 MHz */
|
||||
#define K_MAX 5 /* k loop constraint. 5=533 MHz */
|
||||
#define CL_DEF 2 /* Default value for failsafe operation. 2=CL 4.0 T */
|
||||
#define T_DEF 1 /* Default value for failsafe operation. 1=5ns (cycle time) */
|
||||
|
||||
|
||||
#define BIAS_TCL_T 1
|
||||
#define BIAS_TRP_T 3 /* bias to convert bus clocks to bit field value */
|
||||
#define BIAS_TRRD_T 2
|
||||
#define BIAS_TRCD_T 3
|
||||
#define BIAS_TRAS_T 3
|
||||
#define BIAS_TRC_T 11
|
||||
#define BIAS_TRTP_T 1
|
||||
#define BIAS_TWR_T 3
|
||||
#define BIAS_TWTR_T 0
|
||||
#define BIAS_TFAW_T 7
|
||||
|
||||
#define MIN_TRP_T 3 /* min programmable value in busclocks */
|
||||
#define MAX_TRP_T 6 /* max programmable value in busclocks */
|
||||
#define MIN_TRRD_T 2
|
||||
#define MAX_TRRD_T 5
|
||||
#define MIN_TRCD_T 3
|
||||
#define MAX_TRCD_T 6
|
||||
#define MIN_TRAS_T 5
|
||||
#define MAX_TRAS_T 18
|
||||
#define MIN_TRC_T 11
|
||||
#define MAX_TRC_T 26
|
||||
#define MIN_TRTP_T 2
|
||||
#define MAX_TRTP_T 4
|
||||
#define MIN_TWR_T 3
|
||||
#define MAX_TWR_T 6
|
||||
#define MIN_TWTR_T 1
|
||||
#define MAX_TWTR_T 3
|
||||
|
||||
/* DDR2-1066 support */
|
||||
#define BIAS_TRCD_T_1066 5
|
||||
#define BIAS_TRAS_T_1066 15
|
||||
#define BIAS_TRRD_T_1066 4
|
||||
#define BIAS_TWR_T_1066 4
|
||||
#define BIAS_TRP_T_1066 5
|
||||
#define BIAS_TWTR_T_1066 4
|
||||
|
||||
#define MIN_TRCD_T_1066 5
|
||||
#define MAX_TRCD_T_1066 12
|
||||
#define MIN_TRAS_T_1066 15
|
||||
#define MAX_TRAS_T_1066 30
|
||||
#define MIN_TRC_T_1066 11
|
||||
#define MAX_TRC_T_1066 42
|
||||
#define MIN_TRRD_T_1066 4
|
||||
#define MAX_TRRD_T_1066 7
|
||||
#define MIN_TWR_T_1066 5
|
||||
#define MAX_TWR_T_1066 8
|
||||
#define MIN_TRP_T_1066 5
|
||||
#define MAX_TRP_T_1066 12
|
||||
#define MIN_TWTR_T_1066 4
|
||||
#define MAX_TWTR_T_1066 7
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
* TYPEDEFS, STRUCTURES, ENUMS
|
||||
*
|
||||
*----------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
* FUNCTIONS PROTOTYPE
|
||||
*
|
||||
*----------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
|
||||
#endif /* _MTSPD2_H_ */
|
||||
|
||||
|
||||
Loading…
Reference in New Issue