GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Drop remainders of the removed Totalimpact board. Fix typos. 

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4707 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Uwe Hermann 2009-10-02 00:08:00 +00:00
parent 149d6754aa
commit 5bf864e353
2 changed files with 2 additions and 60 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/mainboard/dell/s1850/Kconfig
View File

@ -1,5 +1,5 @@
config BOARD_DELL_S1850 config BOARD_DELL_S1850
bool "Dell S1850" bool "S1850"
select ARCH_X86 select ARCH_X86
select CPU_INTEL_SOCKET_MPGA604 select CPU_INTEL_SOCKET_MPGA604
select NORTHBRIDGE_INTEL_E7520 select NORTHBRIDGE_INTEL_E7520
@ -8,7 +8,7 @@ config BOARD_DELL_S1850
select SUPERIO_NSC_PC8374 select SUPERIO_NSC_PC8374
select PIRQ_TABLE select PIRQ_TABLE
help help
Dell S1850mainboard. Dell S1850 mainboard.
config MAINBOARD_DIR config MAINBOARD_DIR
string string

58
targets/totalimpact/briq/Config.lb
View File

@ -1,58 +0,0 @@
# Config file for the Total Impact briQ
# This will make a target directory of ./briq
target briq
mainboard totalimpact/briq
## Use stage 1 initialization code
option CONFIG_USE_INIT=1
## We don't use compressed image
option CONFIG_COMPRESS=0
## Turn off POST codes
option CONFIG_NO_POST=1
## Enable serial console
option CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
option CONFIG_CONSOLE_SERIAL8250=1
## Boot linux from IDE
option CONFIG_IDE_PAYLOAD=1
option CONFIG_IDE_BOOT_DRIVE=0
option CONFIG_IDE_SWAB=1
option CONFIG_IDE_OFFSET=0
# ROM is 1Mb
option CONFIG_ROM_SIZE=1024*1024
# Set stack and heap sizes (stage 2)
option CONFIG_STACK_SIZE=0x10000
option CONFIG_HEAP_SIZE=0x10000
# Sandpoint Demo Board
romimage "fallback"
## Base of ROM
option CONFIG_ROMBASE=0xfff00000
## Sandpoint reset vector
option CONFIG_RESET=CONFIG_ROMBASE+0x100
## Exception vectors (other than reset vector)
option CONFIG_EXCEPTION_VECTORS=CONFIG_RESET+0x100
## Start of coreboot in the boot rom
## = CONFIG_RESET + exeception vector table size
option CONFIG_ROMSTART=CONFIG_RESET+0x3100
## Coreboot C code runs at this location in RAM
option CONFIG_RAMBASE=0x00100000
option CONFIG_RAMSTART=0x00100000
option CONFIG_BRIQ_750FX=1
#option CONFIG_BRIQ_7400=1
end
buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback"