soc/intel/tigerlake: Simplify is-device-enabled checks
Simplify if-statements and use is_dev_enabled() where possible. Change-Id: I791273e5dd633cd1d6218b322106e2f62a393259 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43897 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -7,6 +7,7 @@
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#include <arch/smp/mpspec.h>
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#include <cbmem.h>
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci_ops.h>
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#include <ec/google/chromeec/ec.h>
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#include <intelblocks/cpulib.h>
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@ -187,7 +188,7 @@ static unsigned long soc_fill_dmar(unsigned long current)
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uint64_t gfxvtbar = MCHBAR64(GFXVTBAR) & VTBAR_MASK;
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bool gfxvten = MCHBAR32(GFXVTBAR) & VTBAR_ENABLED;
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if (igfx_dev && igfx_dev->enabled && gfxvtbar && gfxvten) {
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if (is_dev_enabled(igfx_dev) && gfxvtbar && gfxvten) {
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unsigned long tmp = current;
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current += acpi_create_dmar_drhd(current, 0, 0, gfxvtbar);
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@ -200,7 +201,7 @@ static unsigned long soc_fill_dmar(unsigned long current)
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uint64_t ipuvtbar = MCHBAR64(IPUVTBAR) & VTBAR_MASK;
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bool ipuvten = MCHBAR32(IPUVTBAR) & VTBAR_ENABLED;
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if (ipu_dev && ipu_dev->enabled && ipuvtbar && ipuvten) {
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if (is_dev_enabled(ipu_dev) && ipuvtbar && ipuvten) {
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unsigned long tmp = current;
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current += acpi_create_dmar_drhd(current, 0, 0, ipuvtbar);
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@ -99,10 +99,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
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/* Check if IGD is present and fill Graphics init param accordingly */
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dev = pcidev_path_on_root(SA_DEVFN_IGD);
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if (CONFIG(RUN_FSP_GOP) && dev && dev->enabled)
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params->PeiGraphicsPeimInit = 1;
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else
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params->PeiGraphicsPeimInit = 0;
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params->PeiGraphicsPeimInit = CONFIG(RUN_FSP_GOP) && is_dev_enabled(dev);
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/* Use coreboot MP PPI services if Kconfig is enabled */
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if (CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI)) {
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@ -195,10 +192,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
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/* SATA */
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dev = pcidev_path_on_root(PCH_DEVFN_SATA);
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if (!dev)
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params->SataEnable = 0;
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else {
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params->SataEnable = dev->enabled;
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params->SataEnable = is_dev_enabled(dev);
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if (params->SataEnable) {
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params->SataMode = config->SataMode;
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params->SataSalpSupport = config->SataSalpSupport;
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memcpy(params->SataPortsEnable, config->SataPortsEnable,
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@ -244,37 +239,22 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
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/* LAN */
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dev = pcidev_path_on_root(PCH_DEVFN_GBE);
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if (!dev)
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params->PchLanEnable = 0;
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else
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params->PchLanEnable = dev->enabled;
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params->PchLanEnable = is_dev_enabled(dev);
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/* CNVi */
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dev = pcidev_path_on_root(PCH_DEVFN_CNVI_WIFI);
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if (dev)
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params->CnviMode = dev->enabled;
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else
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params->CnviMode = 0;
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params->CnviMode = is_dev_enabled(dev);
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/* VMD */
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dev = pcidev_path_on_root(SA_DEVFN_VMD);
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if (dev)
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params->VmdEnable = dev->enabled;
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else
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params->VmdEnable = 0;
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params->VmdEnable = is_dev_enabled(dev);
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/* THC */
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dev = pcidev_path_on_root(PCH_DEVFN_THC0);
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if (!dev)
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params->ThcPort0Assignment = 0;
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else
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params->ThcPort0Assignment = dev->enabled ? THC_0 : THC_NONE;
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params->ThcPort0Assignment = is_dev_enabled(dev) ? THC_0 : THC_NONE;
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dev = pcidev_path_on_root(PCH_DEVFN_THC1);
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if (!dev)
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params->ThcPort1Assignment = 0;
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else
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params->ThcPort1Assignment = dev->enabled ? THC_1 : THC_NONE;
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params->ThcPort1Assignment = is_dev_enabled(dev) ? THC_1 : THC_NONE;
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/* Legacy 8254 timer support */
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params->Enable8254ClockGating = !CONFIG(USE_LEGACY_8254_TIMER);
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@ -3,6 +3,7 @@
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#include <assert.h>
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#include <console/console.h>
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#include <cpu/x86/msr.h>
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#include <device/device.h>
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#include <fsp/util.h>
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#include <intelblocks/cpulib.h>
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#include <intelblocks/mp_init.h>
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@ -21,16 +22,13 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
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uint32_t cpu_id, mask = 0;
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const struct device *dev;
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/*
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* If IGD is enabled, set IGD stolen size to 60MB.
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* Otherwise, skip IGD init in FSP.
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*/
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dev = pcidev_path_on_root(SA_DEVFN_IGD);
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if (!dev || !dev->enabled) {
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/* Skip IGD initialization in FSP if device is disabled in devicetree.cb */
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m_cfg->InternalGfx = 0;
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m_cfg->IgdDvmt50PreAlloc = 0;
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} else {
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m_cfg->InternalGfx = 1;
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/* Set IGD stolen size to 60MB. */
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m_cfg->IgdDvmt50PreAlloc = 0xFE;
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}
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m_cfg->InternalGfx = is_dev_enabled(dev);
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m_cfg->IgdDvmt50PreAlloc = m_cfg->InternalGfx ? 0xFE : 0;
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m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE;
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m_cfg->IedSize = CONFIG_IED_REGION_SIZE;
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@ -76,7 +74,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
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/* TraceHub configuration */
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dev = pcidev_path_on_root(PCH_DEVFN_TRACEHUB);
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if (dev && dev->enabled && config->TraceHubMode) {
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if (is_dev_enabled(dev) && config->TraceHubMode) {
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m_cfg->PcdDebugInterfaceFlags |= DEBUG_INTERFACE_TRACEHUB;
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m_cfg->PchTraceHubMode = config->TraceHubMode;
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m_cfg->CpuTraceHubMode = config->TraceHubMode;
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@ -87,10 +85,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
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/* ISH */
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dev = pcidev_path_on_root(PCH_DEVFN_ISH);
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if (!dev || !dev->enabled)
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m_cfg->PchIshEnable = 0;
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else
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m_cfg->PchIshEnable = 1;
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m_cfg->PchIshEnable = is_dev_enabled(dev);
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/* DP port config */
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m_cfg->DdiPortAConfig = config->DdiPortAConfig;
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@ -119,39 +114,23 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
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/* TCSS DMA */
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dev = pcidev_path_on_root(SA_DEVFN_TCSS_DMA0);
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if (dev)
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m_cfg->TcssDma0En = dev->enabled;
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else
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m_cfg->TcssDma0En = 0;
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m_cfg->TcssDma0En = is_dev_enabled(dev);
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dev = pcidev_path_on_root(SA_DEVFN_TCSS_DMA1);
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if (dev)
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m_cfg->TcssDma1En = dev->enabled;
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else
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m_cfg->TcssDma1En = 0;
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m_cfg->TcssDma1En = is_dev_enabled(dev);
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/* USB4/TBT */
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dev = pcidev_path_on_root(SA_DEVFN_TBT0);
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if (dev)
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m_cfg->TcssItbtPcie0En = dev->enabled;
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else
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m_cfg->TcssItbtPcie0En = 0;
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m_cfg->TcssItbtPcie0En = is_dev_enabled(dev);
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dev = pcidev_path_on_root(SA_DEVFN_TBT1);
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if (dev)
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m_cfg->TcssItbtPcie1En = dev->enabled;
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else
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m_cfg->TcssItbtPcie1En = 0;
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m_cfg->TcssItbtPcie1En = is_dev_enabled(dev);
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dev = pcidev_path_on_root(SA_DEVFN_TBT2);
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if (dev)
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m_cfg->TcssItbtPcie2En = dev->enabled;
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else
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m_cfg->TcssItbtPcie2En = 0;
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m_cfg->TcssItbtPcie2En = is_dev_enabled(dev);
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dev = pcidev_path_on_root(SA_DEVFN_TBT3);
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if (dev)
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m_cfg->TcssItbtPcie3En = dev->enabled;
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else
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m_cfg->TcssItbtPcie3En = 0;
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m_cfg->TcssItbtPcie3En = is_dev_enabled(dev);
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/* Hyper Threading */
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m_cfg->HyperThreading = !config->HyperThreadingDisable;
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@ -167,10 +146,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
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/* Audio: HDAUDIO_LINK_MODE I2S/SNDW */
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dev = pcidev_path_on_root(PCH_DEVFN_HDA);
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if (!dev)
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m_cfg->PchHdaEnable = 0;
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else
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m_cfg->PchHdaEnable = dev->enabled;
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m_cfg->PchHdaEnable = is_dev_enabled(dev);
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m_cfg->PchHdaDspEnable = config->PchHdaDspEnable;
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m_cfg->PchHdaAudioLinkHdaEnable = config->PchHdaAudioLinkHdaEnable;
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