nb/intel/sandybridge: Add warning to saved structs
When changing any of the structures that are cached in non-volatile storage, it is necessary to bump MRC_CACHE_VERSION so that the old information is not misinterpreted. Change-Id: Idefbc38b3a8198b1b5909e775b3c289db689fc0c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39756 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -33,8 +33,6 @@
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#include "raminit_common.h"
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#include "sandybridge.h"
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#define MRC_CACHE_VERSION 1
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/* FIXME: no ECC support */
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/* FIXME: no support for 3-channel chipsets */
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@ -41,15 +41,22 @@
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performant and even 1 seems to be enough in practice. */
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#define NUM_PATTERNS 4
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/*
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* WARNING: Do not forget to increase MRC_CACHE_VERSION when the saved data is changed!
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*/
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#define MRC_CACHE_VERSION 1
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typedef struct odtmap_st {
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u16 rttwr;
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u16 rttnom;
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} odtmap;
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/* WARNING: Do not forget to increase MRC_CACHE_VERSION when this struct is changed! */
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typedef struct dimm_info_st {
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dimm_attr dimm[NUM_CHANNELS][NUM_SLOTS];
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} dimm_info;
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/* WARNING: Do not forget to increase MRC_CACHE_VERSION when this struct is changed! */
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struct ram_rank_timings {
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/* ROUNDT_LAT register: One byte per slotrank */
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u8 roundtrip_latency;
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@ -72,6 +79,7 @@ struct ram_rank_timings {
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} lanes[NUM_LANES];
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};
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/* WARNING: Do not forget to increase MRC_CACHE_VERSION when this struct is changed! */
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typedef struct ramctr_timing_st {
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u16 spd_crc[NUM_CHANNELS][NUM_SLOTS];
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int sandybridge;
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