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mb/tglrvp: Configure intel common config 

Configure lockdown and i2c speed setting.

BUG🅱️151161585
BRANCH=none
TEST=build and boot tglrvp and check FSP logs to lockdown
parameters

Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: Id7a1e9bd94ff86faa390b5de0518e8b3cb668bff
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40116
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Wonkyu Kim 2020-04-03 00:42:22 -07:00 committed by Patrick Georgi
parent cae9887996
commit 5c27182366
2 changed files with 40 additions and 0 deletions
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20
src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
View File

@ -128,6 +128,26 @@ chip soc/intel/tigerlake
# Not disconnected/enumerable
register "PchHdaIDispCodecDisconnect" = "0"
# Intel Common SoC Config
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
.i2c[0] = {
.speed = I2C_SPEED_FAST,
},
.i2c[1] = {
.speed = I2C_SPEED_FAST,
},
.i2c[2] = {
.speed = I2C_SPEED_FAST,
},
.i2c[3] = {
.speed = I2C_SPEED_FAST,
},
.i2c[5] = {
.speed = I2C_SPEED_FAST,
},
}"
device domain 0 on
#From EDS(575683)
device pci 00.0 on end # Host Bridge 0x9A14:U/0x9A12:Y

20
src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
View File

@ -124,6 +124,26 @@ chip soc/intel/tigerlake
# Not disconnected/enumerable
register "PchHdaIDispCodecDisconnect" = "0"
# Intel Common SoC Config
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
.i2c[0] = {
.speed = I2C_SPEED_FAST,
},
.i2c[1] = {
.speed = I2C_SPEED_FAST,
},
.i2c[2] = {
.speed = I2C_SPEED_FAST,
},
.i2c[3] = {
.speed = I2C_SPEED_FAST,
},
.i2c[5] = {
.speed = I2C_SPEED_FAST,
},
}"
device domain 0 on
#From EDS(575683)
device pci 00.0 on end # Host Bridge 0x9A14:U/0x9A12:Y