mb/tglrvp: Configure intel common config
Configure lockdown and i2c speed setting. BUG🅱️151161585 BRANCH=none TEST=build and boot tglrvp and check FSP logs to lockdown parameters Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: Id7a1e9bd94ff86faa390b5de0518e8b3cb668bff Reviewed-on: https://review.coreboot.org/c/coreboot/+/40116 Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -128,6 +128,26 @@ chip soc/intel/tigerlake
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# Not disconnected/enumerable
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# Not disconnected/enumerable
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register "PchHdaIDispCodecDisconnect" = "0"
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register "PchHdaIDispCodecDisconnect" = "0"
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# Intel Common SoC Config
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register "common_soc_config" = "{
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.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
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.i2c[0] = {
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.speed = I2C_SPEED_FAST,
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},
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.i2c[1] = {
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.speed = I2C_SPEED_FAST,
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},
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.i2c[2] = {
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.speed = I2C_SPEED_FAST,
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},
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.i2c[3] = {
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.speed = I2C_SPEED_FAST,
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},
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.i2c[5] = {
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.speed = I2C_SPEED_FAST,
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},
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}"
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device domain 0 on
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device domain 0 on
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#From EDS(575683)
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#From EDS(575683)
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device pci 00.0 on end # Host Bridge 0x9A14:U/0x9A12:Y
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device pci 00.0 on end # Host Bridge 0x9A14:U/0x9A12:Y
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@ -124,6 +124,26 @@ chip soc/intel/tigerlake
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# Not disconnected/enumerable
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# Not disconnected/enumerable
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register "PchHdaIDispCodecDisconnect" = "0"
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register "PchHdaIDispCodecDisconnect" = "0"
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# Intel Common SoC Config
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register "common_soc_config" = "{
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.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
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.i2c[0] = {
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.speed = I2C_SPEED_FAST,
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},
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.i2c[1] = {
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.speed = I2C_SPEED_FAST,
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},
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.i2c[2] = {
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.speed = I2C_SPEED_FAST,
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},
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.i2c[3] = {
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.speed = I2C_SPEED_FAST,
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},
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.i2c[5] = {
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.speed = I2C_SPEED_FAST,
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},
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}"
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device domain 0 on
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device domain 0 on
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#From EDS(575683)
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#From EDS(575683)
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device pci 00.0 on end # Host Bridge 0x9A14:U/0x9A12:Y
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device pci 00.0 on end # Host Bridge 0x9A14:U/0x9A12:Y
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