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buildsystem: Promote rules.h to default include 

Does not fix 3rdparty/, *.S or *.ld or yet.

Change-Id: I66b48013dd89540b35ab219d2b64bc13f5f19cda
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/17656
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Kyösti Mälkki 2016-11-30 14:53:24 +02:00 committed by Patrick Georgi
parent f86baf3e90
commit 5c29daa150
98 changed files with 1 additions and 97 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
Makefile.inc
View File

@ -383,6 +383,7 @@ CPPFLAGS_common += -Isrc/device/oprom/include
VBOOT_SOURCE ?= 3rdparty/vboot VBOOT_SOURCE ?= 3rdparty/vboot
CPPFLAGS_common += -I$(VBOOT_SOURCE)/firmware/include CPPFLAGS_common += -I$(VBOOT_SOURCE)/firmware/include
CPPFLAGS_common += -include $(src)/include/kconfig.h CPPFLAGS_common += -include $(src)/include/kconfig.h
CPPFLAGS_common += -include $(src)/include/rules.h
CPPFLAGS_common += -include $(src)/commonlib/include/commonlib/compiler.h CPPFLAGS_common += -include $(src)/commonlib/include/commonlib/compiler.h
CPPFLAGS_common += -I3rdparty CPPFLAGS_common += -I3rdparty
CPPFLAGS_common += -D__BUILD_DIR__=\"$(obj)\" CPPFLAGS_common += -D__BUILD_DIR__=\"$(obj)\"

1
src/arch/arm64/boot.c
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@ -19,7 +19,6 @@
#include <arch/transition.h> #include <arch/transition.h>
#include <arm_tf.h> #include <arm_tf.h>
#include <program_loading.h> #include <program_loading.h>
#include <rules.h>
#include <string.h> #include <string.h>
static void run_payload(struct prog *prog) static void run_payload(struct prog *prog)

1
src/arch/riscv/boot.c
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@ -17,7 +17,6 @@
#include <vm.h> #include <vm.h>
#include <arch/boot.h> #include <arch/boot.h>
#include <arch/encoding.h> #include <arch/encoding.h>
#include <rules.h>
#include <console/console.h> #include <console/console.h>
#include <arch/smp/smp.h> #include <arch/smp/smp.h>

1
src/arch/riscv/stages.c
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@ -28,7 +28,6 @@
#include <arch/encoding.h> #include <arch/encoding.h>
#include <arch/stages.h> #include <arch/stages.h>
#include <arch/smp/smp.h> #include <arch/smp/smp.h>
#include <rules.h>
void stage_entry(void) void stage_entry(void)
{ {

1
src/arch/x86/acpi_s3.c
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@ -22,7 +22,6 @@
#include <timestamp.h> #include <timestamp.h>
#include <program_loading.h> #include <program_loading.h>
#include <romstage_handoff.h> #include <romstage_handoff.h>
#include <rules.h>
#include <symbols.h> #include <symbols.h>
#if ENV_RAMSTAGE || ENV_POSTCAR #if ENV_RAMSTAGE || ENV_POSTCAR

1
src/arch/x86/exception.c
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@ -19,7 +19,6 @@
#include <console/streams.h> #include <console/streams.h>
#include <cpu/x86/cr.h> #include <cpu/x86/cr.h>
#include <cpu/x86/lapic.h> #include <cpu/x86/lapic.h>
#include <rules.h>
#include <stdint.h> #include <stdint.h>
#include <string.h> #include <string.h>

1
src/arch/x86/include/arch/acpi.h
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@ -57,7 +57,6 @@
#if !defined(__ASSEMBLER__) && !defined(__ACPI__) && !defined(__ROMCC__) #if !defined(__ASSEMBLER__) && !defined(__ACPI__) && !defined(__ROMCC__)
#include <stdint.h> #include <stdint.h>
#include <rules.h>
#include <commonlib/helpers.h> #include <commonlib/helpers.h>
#include <device/device.h> #include <device/device.h>
#include <uuid.h> #include <uuid.h>

1
src/arch/x86/include/arch/cpu.h
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@ -16,7 +16,6 @@
#include <stdint.h> #include <stdint.h>
#include <stddef.h> #include <stddef.h>
#include <rules.h>
/* /*
* EFLAGS bits * EFLAGS bits

1
src/arch/x86/include/arch/early_variables.h
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@ -18,7 +18,6 @@
#include <arch/symbols.h> #include <arch/symbols.h>
#include <stdlib.h> #include <stdlib.h>
#include <rules.h>
#if ENV_CACHE_AS_RAM && !IS_ENABLED(CONFIG_NO_CAR_GLOBAL_MIGRATION) #if ENV_CACHE_AS_RAM && !IS_ENABLED(CONFIG_NO_CAR_GLOBAL_MIGRATION)
asm(".section .car.global_data,\"w\",@nobits"); asm(".section .car.global_data,\"w\",@nobits");

1
src/arch/x86/include/arch/exception.h
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@ -31,7 +31,6 @@
#define _ARCH_EXCEPTION_H #define _ARCH_EXCEPTION_H
#include <arch/cpu.h> #include <arch/cpu.h>
#include <rules.h>
#if IS_ENABLED(CONFIG_IDT_IN_EVERY_STAGE) || ENV_RAMSTAGE #if IS_ENABLED(CONFIG_IDT_IN_EVERY_STAGE) || ENV_RAMSTAGE
asmlinkage void exception_init(void); asmlinkage void exception_init(void);

1
src/arch/x86/include/arch/io.h
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@ -16,7 +16,6 @@
#include <endian.h> #include <endian.h>
#include <stdint.h> #include <stdint.h>
#include <rules.h>
#include <device/pci_type.h> #include <device/pci_type.h>
/* /*

1
src/arch/x86/include/arch/memlayout.h
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@ -16,7 +16,6 @@
#ifndef __ARCH_MEMLAYOUT_H #ifndef __ARCH_MEMLAYOUT_H
#define __ARCH_MEMLAYOUT_H #define __ARCH_MEMLAYOUT_H
#include <rules.h>
#if ENV_BOOTBLOCK || ENV_ROMSTAGE || ENV_VERSTAGE #if ENV_BOOTBLOCK || ENV_ROMSTAGE || ENV_VERSTAGE
/* No .data or .bss sections. Cache as RAM is handled separately. */ /* No .data or .bss sections. Cache as RAM is handled separately. */

1
src/arch/x86/rdrand.c
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@ -14,7 +14,6 @@
*/ */
#include <random.h> #include <random.h>
#include <rules.h>
/* /*
* Intel recommends that applications attempt 10 retries in a tight loop * Intel recommends that applications attempt 10 retries in a tight loop

1
src/commonlib/storage/pci_sdhci.c
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@ -13,7 +13,6 @@
* GNU General Public License for more details. * GNU General Public License for more details.
*/ */
#include <rules.h>
#if ENV_RAMSTAGE #if ENV_RAMSTAGE
#define __SIMPLE_DEVICE__ 1 #define __SIMPLE_DEVICE__ 1
#endif #endif

1
src/console/console.c
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@ -22,7 +22,6 @@
#include <console/usb.h> #include <console/usb.h>
#include <console/spi.h> #include <console/spi.h>
#include <console/flash.h> #include <console/flash.h>
#include <rules.h>
void console_hw_init(void) void console_hw_init(void)
{ {

1
src/console/init.c
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@ -20,7 +20,6 @@
#include <console/streams.h> #include <console/streams.h>
#include <device/pci.h> #include <device/pci.h>
#include <option.h> #include <option.h>
#include <rules.h>
#include <version.h> #include <version.h>
/* Mutable console log level only allowed when RAM comes online. */ /* Mutable console log level only allowed when RAM comes online. */

1
src/console/post.c
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@ -20,7 +20,6 @@
#include <device/device.h> #include <device/device.h>
#include <pc80/mc146818rtc.h> #include <pc80/mc146818rtc.h>
#include <smp/spinlock.h> #include <smp/spinlock.h>
#include <rules.h>
/* Write POST information */ /* Write POST information */

1
src/cpu/intel/microcode/microcode.c
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@ -27,7 +27,6 @@
#include <arch/cpu.h> #include <arch/cpu.h>
#include <cpu/x86/msr.h> #include <cpu/x86/msr.h>
#include <cpu/intel/microcode.h> #include <cpu/intel/microcode.h>
#include <rules.h>
#if !defined(__PRE_RAM__) #if !defined(__PRE_RAM__)
#include <smp/spinlock.h> #include <smp/spinlock.h>

1
src/cpu/x86/32bit/entry32.inc
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@ -15,7 +15,6 @@
#include <arch/rom_segs.h> #include <arch/rom_segs.h>
#include <cpu/x86/post_code.h> #include <cpu/x86/post_code.h>
#include <rules.h>
#include <arch/x86/gdt_init.S> #include <arch/x86/gdt_init.S>
.code32 .code32

1
src/cpu/x86/pae/pgtbl.c
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@ -20,7 +20,6 @@
#include <cpu/x86/cr.h> #include <cpu/x86/cr.h>
#include <cpu/x86/msr.h> #include <cpu/x86/msr.h>
#include <cpu/x86/pae.h> #include <cpu/x86/pae.h>
#include <rules.h>
#include <string.h> #include <string.h>
#include <symbols.h> #include <symbols.h>

1
src/drivers/intel/fsp1_1/cache_as_ram.inc
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@ -24,7 +24,6 @@
* performs the final stage of initialization. * performs the final stage of initialization.
*/ */
#include <rules.h>
#define LHLT_DELAY 0x50000 /* I/O delay between post codes on failure */ #define LHLT_DELAY 0x50000 /* I/O delay between post codes on failure */

1
src/drivers/intel/fsp1_1/include/fsp/util.h
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@ -17,7 +17,6 @@
#ifndef FSP1_1_UTIL_H #ifndef FSP1_1_UTIL_H
#define FSP1_1_UTIL_H #define FSP1_1_UTIL_H
#include <rules.h>
#include <fsp/api.h> #include <fsp/api.h>
/* Current users expect to get the SoC's FSP definitions by including util.h. */ /* Current users expect to get the SoC's FSP definitions by including util.h. */
#include <fsp/soc_binding.h> #include <fsp/soc_binding.h>

1
src/drivers/intel/fsp2_0/include/fsp/info_header.h
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@ -13,7 +13,6 @@
#ifndef _FSP2_0_INFO_HEADER_H_ #ifndef _FSP2_0_INFO_HEADER_H_
#define _FSP2_0_INFO_HEADER_H_ #define _FSP2_0_INFO_HEADER_H_
#include <rules.h>
#include <stdint.h> #include <stdint.h>
#include <stdlib.h> #include <stdlib.h>
#include <types.h> #include <types.h>

1
src/drivers/net/ne2k.c
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@ -34,7 +34,6 @@ SMC8416 PIO support added by Andrew Bettison (andrewb@zip.com.au) on 4/3/02
#include <device/pci.h> #include <device/pci.h>
#include <device/pci_ids.h> #include <device/pci_ids.h>
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include <rules.h>
#include <stdlib.h> #include <stdlib.h>
#include <string.h> #include <string.h>
#include <ip_checksum.h> #include <ip_checksum.h>

1
src/drivers/spi/spi_flash.c
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@ -12,7 +12,6 @@
#include <boot_device.h> #include <boot_device.h>
#include <cpu/x86/smm.h> #include <cpu/x86/smm.h>
#include <delay.h> #include <delay.h>
#include <rules.h>
#include <stdlib.h> #include <stdlib.h>
#include <string.h> #include <string.h>
#include <spi-generic.h> #include <spi-generic.h>

1
src/drivers/uart/uart8250io.c
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@ -14,7 +14,6 @@
* GNU General Public License for more details. * GNU General Public License for more details.
*/ */
#include <rules.h>
#include <stdlib.h> #include <stdlib.h>
#include <arch/io.h> #include <arch/io.h>
#include <boot/coreboot_tables.h> #include <boot/coreboot_tables.h>

1
src/drivers/uart/uart8250mem.c
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@ -19,7 +19,6 @@
#include <console/uart.h> #include <console/uart.h>
#include <device/device.h> #include <device/device.h>
#include <delay.h> #include <delay.h>
#include <rules.h>
#include <stdint.h> #include <stdint.h>
#include "uart8250reg.h" #include "uart8250reg.h"

1
src/include/bootstate.h
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@ -15,7 +15,6 @@
#ifndef BOOTSTATE_H #ifndef BOOTSTATE_H
#define BOOTSTATE_H #define BOOTSTATE_H
#include <rules.h>
#include <string.h> #include <string.h>
#include <stdlib.h> #include <stdlib.h>
#include <stddef.h> #include <stddef.h>

1
src/include/cbmem.h
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@ -18,7 +18,6 @@
#define _CBMEM_H_ #define _CBMEM_H_
#include <commonlib/cbmem_id.h> #include <commonlib/cbmem_id.h>
#include <rules.h>
#include <stddef.h> #include <stddef.h>
#include <stdint.h> #include <stdint.h>
#include <boot/coreboot_tables.h> #include <boot/coreboot_tables.h>

1
src/include/console/cbmem_console.h
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@ -15,7 +15,6 @@
#ifndef _CONSOLE_CBMEM_CONSOLE_H_ #ifndef _CONSOLE_CBMEM_CONSOLE_H_
#define _CONSOLE_CBMEM_CONSOLE_H_ #define _CONSOLE_CBMEM_CONSOLE_H_
#include <rules.h>
#include <stdint.h> #include <stdint.h>
void cbmemc_init(void); void cbmemc_init(void);

1
src/include/console/console.h
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@ -17,7 +17,6 @@
#define CONSOLE_CONSOLE_H_ #define CONSOLE_CONSOLE_H_
#include <stdint.h> #include <stdint.h>
#include <rules.h>
#include <arch/cpu.h> #include <arch/cpu.h>
#include <console/post_codes.h> #include <console/post_codes.h>
#include <commonlib/loglevel.h> #include <commonlib/loglevel.h>

1
src/include/console/flash.h
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@ -16,7 +16,6 @@
#ifndef CONSOLE_FLASH_H #ifndef CONSOLE_FLASH_H
#define CONSOLE_FLASH_H 1 #define CONSOLE_FLASH_H 1
#include <rules.h>
#include <stdint.h> #include <stdint.h>
void flashconsole_init(void); void flashconsole_init(void);

1
src/include/console/ne2k.h
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@ -16,7 +16,6 @@
#ifndef _NE2K_H__ #ifndef _NE2K_H__
#define _NE2K_H__ #define _NE2K_H__
#include <rules.h>
#include <stdint.h> #include <stdint.h>
void ne2k_append_data(unsigned char *d, int len, unsigned int base); void ne2k_append_data(unsigned char *d, int len, unsigned int base);

1
src/include/console/qemu_debugcon.h
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@ -1,7 +1,6 @@
#ifndef _QEMU_DEBUGCON_H_ #ifndef _QEMU_DEBUGCON_H_
#define _QEMU_DEBUGCON_H_ #define _QEMU_DEBUGCON_H_
#include <rules.h>
#include <stdint.h> #include <stdint.h>
void qemu_debugcon_init(void); void qemu_debugcon_init(void);

1
src/include/console/spi.h
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@ -16,7 +16,6 @@
#ifndef CONSOLE_SPI_H #ifndef CONSOLE_SPI_H
#define CONSOLE_SPI_H 1 #define CONSOLE_SPI_H 1
#include <rules.h>
#include <stdint.h> #include <stdint.h>
void spiconsole_init(void); void spiconsole_init(void);

1
src/include/console/spkmodem.h
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@ -1,7 +1,6 @@
#ifndef SPKMODEM_H #ifndef SPKMODEM_H
#define SPKMODEM_H 1 #define SPKMODEM_H 1
#include <rules.h>
#include <stdint.h> #include <stdint.h>
void spkmodem_init(void); void spkmodem_init(void);

1
src/include/console/uart.h
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@ -16,7 +16,6 @@
#ifndef CONSOLE_UART_H #ifndef CONSOLE_UART_H
#define CONSOLE_UART_H #define CONSOLE_UART_H
#include <rules.h>
#include <stdint.h> #include <stdint.h>
/* Return the clock frequency UART uses as reference clock for /* Return the clock frequency UART uses as reference clock for

1
src/include/console/usb.h
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@ -17,7 +17,6 @@
#ifndef _CONSOLE_USB_H_ #ifndef _CONSOLE_USB_H_
#define _CONSOLE_USB_H_ #define _CONSOLE_USB_H_
#include <rules.h>
#include <stdint.h> #include <stdint.h>
void usbdebug_init(void); void usbdebug_init(void);

1
src/include/device/device.h
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@ -11,7 +11,6 @@
#include <stdint.h> #include <stdint.h>
#include <stddef.h> #include <stddef.h>
#include <rules.h>
#include <device/resource.h> #include <device/resource.h>
#include <device/path.h> #include <device/path.h>
#include <device/pci_type.h> #include <device/pci_type.h>

1
src/include/device/pci.h
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@ -19,7 +19,6 @@
#include <stdint.h> #include <stdint.h>
#include <stddef.h> #include <stddef.h>
#include <rules.h>
#include <arch/io.h> #include <arch/io.h>
#include <device/pci_def.h> #include <device/pci_def.h>
#include <device/resource.h> #include <device/resource.h>

1
src/include/device/pnp.h
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@ -2,7 +2,6 @@
#define DEVICE_PNP_H #define DEVICE_PNP_H
#include <stdint.h> #include <stdint.h>
#include <rules.h>
#include <device/device.h> #include <device/device.h>
#include <device/pnp_def.h> #include <device/pnp_def.h>
#include <arch/io.h> #include <arch/io.h>

1
src/include/memlayout.h
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@ -18,7 +18,6 @@
#ifndef __MEMLAYOUT_H #ifndef __MEMLAYOUT_H
#define __MEMLAYOUT_H #define __MEMLAYOUT_H
#include <rules.h>
#include <arch/memlayout.h> #include <arch/memlayout.h>
/* Macros that the architecture can override. */ /* Macros that the architecture can override. */

1
src/include/stddef.h
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@ -2,7 +2,6 @@
#define STDDEF_H #define STDDEF_H
#include <commonlib/helpers.h> #include <commonlib/helpers.h>
#include <rules.h>
typedef long ptrdiff_t; typedef long ptrdiff_t;
#ifndef __SIZE_TYPE__ #ifndef __SIZE_TYPE__

1
src/lib/bootmode.c
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@ -13,7 +13,6 @@
* GNU General Public License for more details. * GNU General Public License for more details.
*/ */
#include <rules.h>
#include <bootmode.h> #include <bootmode.h>
#include <vendorcode/google/chromeos/chromeos.h> #include <vendorcode/google/chromeos/chromeos.h>

1
src/lib/cbmem_common.c
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@ -15,7 +15,6 @@
#include <cbmem.h> #include <cbmem.h>
#include <bootstate.h> #include <bootstate.h>
#include <rules.h>
#include <symbols.h> #include <symbols.h>
void cbmem_run_init_hooks(int is_recovery) void cbmem_run_init_hooks(int is_recovery)

1
src/lib/ext_stage_cache.c
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@ -18,7 +18,6 @@
#include <cbmem.h> #include <cbmem.h>
#include <console/console.h> #include <console/console.h>
#include <imd.h> #include <imd.h>
#include <rules.h>
#include <stage_cache.h> #include <stage_cache.h>
#include <string.h> #include <string.h>

1
src/lib/imd_cbmem.c
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@ -18,7 +18,6 @@
#include <console/console.h> #include <console/console.h>
#include <cbmem.h> #include <cbmem.h>
#include <imd.h> #include <imd.h>
#include <rules.h>
#include <string.h> #include <string.h>
#include <stdlib.h> #include <stdlib.h>
#include <arch/early_variables.h> #include <arch/early_variables.h>

1
src/lib/prog_loaders.c
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@ -25,7 +25,6 @@
#include <reset.h> #include <reset.h>
#include <romstage_handoff.h> #include <romstage_handoff.h>
#include <rmodule.h> #include <rmodule.h>
#include <rules.h>
#include <stage_cache.h> #include <stage_cache.h>
#include <symbols.h> #include <symbols.h>
#include <timestamp.h> #include <timestamp.h>

1
src/lib/romstage_handoff.c
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@ -18,7 +18,6 @@
#include <cbmem.h> #include <cbmem.h>
#include <console/console.h> #include <console/console.h>
#include <romstage_handoff.h> #include <romstage_handoff.h>
#include <rules.h>
struct romstage_handoff { struct romstage_handoff {
/* Indicate if the current boot is an S3 resume. If /* Indicate if the current boot is an S3 resume. If

1
src/lib/timestamp.c
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@ -23,7 +23,6 @@
#include <timer.h> #include <timer.h>
#include <timestamp.h> #include <timestamp.h>
#include <arch/early_variables.h> #include <arch/early_variables.h>
#include <rules.h>
#include <smp/node.h> #include <smp/node.h>
#define MAX_TIMESTAMPS 192 #define MAX_TIMESTAMPS 192

1
src/mainboard/google/cyan/chromeos.c
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@ -15,7 +15,6 @@
*/ */
#include <arch/io.h> #include <arch/io.h>
#include <rules.h>
#include <gpio.h> #include <gpio.h>
#include <soc/gpio.h> #include <soc/gpio.h>
#include <string.h> #include <string.h>

1
src/mainboard/google/dragonegg/chromeos.c
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@ -16,7 +16,6 @@
#include <arch/acpi.h> #include <arch/acpi.h>
#include <baseboard/variants.h> #include <baseboard/variants.h>
#include <gpio.h> #include <gpio.h>
#include <rules.h>
#include <soc/gpio.h> #include <soc/gpio.h>
#include <vendorcode/google/chromeos/chromeos.h> #include <vendorcode/google/chromeos/chromeos.h>

1
src/mainboard/google/eve/chromeos.c
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@ -14,7 +14,6 @@
* GNU General Public License for more details. * GNU General Public License for more details.
*/ */
#include <rules.h>
#include <gpio.h> #include <gpio.h>
#include <soc/gpio.h> #include <soc/gpio.h>
#include <vendorcode/google/chromeos/chromeos.h> #include <vendorcode/google/chromeos/chromeos.h>

1
src/mainboard/google/fizz/chromeos.c
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@ -14,7 +14,6 @@
*/ */
#include <gpio.h> #include <gpio.h>
#include <rules.h>
#include <baseboard/variants.h> #include <baseboard/variants.h>
#include <soc/gpio.h> #include <soc/gpio.h>
#include <vendorcode/google/chromeos/chromeos.h> #include <vendorcode/google/chromeos/chromeos.h>

1
src/mainboard/google/glados/chromeos.c
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@ -14,7 +14,6 @@
* GNU General Public License for more details. * GNU General Public License for more details.
*/ */
#include <rules.h>
#include <gpio.h> #include <gpio.h>
#include <soc/gpio.h> #include <soc/gpio.h>
#include <string.h> #include <string.h>

1
src/mainboard/google/kahlee/ec.c
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@ -16,7 +16,6 @@
#include <arch/acpi.h> #include <arch/acpi.h>
#include <console/console.h> #include <console/console.h>
#include <ec/google/chromeec/ec.h> #include <ec/google/chromeec/ec.h>
#include <rules.h>
#include <soc/southbridge.h> #include <soc/southbridge.h>
#include <variant/ec.h> #include <variant/ec.h>

1
src/mainboard/google/octopus/ec.c
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@ -19,7 +19,6 @@
#include <ec/ec.h> #include <ec/ec.h>
#include <ec/google/chromeec/ec.h> #include <ec/google/chromeec/ec.h>
#include <intelblocks/lpc_lib.h> #include <intelblocks/lpc_lib.h>
#include <rules.h>
#include <variant/ec.h> #include <variant/ec.h>
static void ramstage_ec_init(void) static void ramstage_ec_init(void)

1
src/mainboard/google/poppy/chromeos.c
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@ -16,7 +16,6 @@
#include <arch/acpi.h> #include <arch/acpi.h>
#include <baseboard/variants.h> #include <baseboard/variants.h>
#include <gpio.h> #include <gpio.h>
#include <rules.h>
#include <soc/gpio.h> #include <soc/gpio.h>
#include <vendorcode/google/chromeos/chromeos.h> #include <vendorcode/google/chromeos/chromeos.h>

1
src/mainboard/google/reef/ec.c
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@ -18,7 +18,6 @@
#include <ec/ec.h> #include <ec/ec.h>
#include <ec/google/chromeec/ec.h> #include <ec/google/chromeec/ec.h>
#include <intelblocks/lpc_lib.h> #include <intelblocks/lpc_lib.h>
#include <rules.h>
#include <variant/ec.h> #include <variant/ec.h>
static void ramstage_ec_init(void) static void ramstage_ec_init(void)

1
src/mainboard/google/sarien/chromeos.c
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@ -16,7 +16,6 @@
#include <arch/acpi.h> #include <arch/acpi.h>
#include <boot/coreboot_tables.h> #include <boot/coreboot_tables.h>
#include <gpio.h> #include <gpio.h>
#include <rules.h>
#include <soc/gpio.h> #include <soc/gpio.h>
#include <variant/gpio.h> #include <variant/gpio.h>
#include <vendorcode/google/chromeos/chromeos.h> #include <vendorcode/google/chromeos/chromeos.h>

1
src/mainboard/google/storm/mmu.c
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@ -11,7 +11,6 @@
*/ */
#include <arch/cache.h> #include <arch/cache.h>
#include <rules.h>
#include <soc/soc_services.h> #include <soc/soc_services.h>
#include <symbols.h> #include <symbols.h>
#include "mmu.h" #include "mmu.h"

1
src/mainboard/intel/cannonlake_rvp/chromeos.c
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@ -16,7 +16,6 @@
#include <arch/acpi.h> #include <arch/acpi.h>
#include <baseboard/variants.h> #include <baseboard/variants.h>
#include <gpio.h> #include <gpio.h>
#include <rules.h>
#include <soc/gpio.h> #include <soc/gpio.h>
#include <variant/gpio.h> #include <variant/gpio.h>
#include <vendorcode/google/chromeos/chromeos.h> #include <vendorcode/google/chromeos/chromeos.h>

1
src/mainboard/intel/coffeelake_rvp/chromeos.c
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@ -16,7 +16,6 @@
#include <arch/acpi.h> #include <arch/acpi.h>
#include <baseboard/variants.h> #include <baseboard/variants.h>
#include <gpio.h> #include <gpio.h>
#include <rules.h>
#include <soc/gpio.h> #include <soc/gpio.h>
#include <vendorcode/google/chromeos/chromeos.h> #include <vendorcode/google/chromeos/chromeos.h>

1
src/mainboard/intel/glkrvp/ec.c
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@ -19,7 +19,6 @@
#include <ec/ec.h> #include <ec/ec.h>
#include <ec/google/chromeec/ec.h> #include <ec/google/chromeec/ec.h>
#include <intelblocks/lpc_lib.h> #include <intelblocks/lpc_lib.h>
#include <rules.h>
#include <variant/ec.h> #include <variant/ec.h>
static void ramstage_ec_init(void) static void ramstage_ec_init(void)

1
src/mainboard/intel/icelake_rvp/chromeos.c
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@ -16,7 +16,6 @@
#include <arch/acpi.h> #include <arch/acpi.h>
#include <baseboard/variants.h> #include <baseboard/variants.h>
#include <gpio.h> #include <gpio.h>
#include <rules.h>
#include <soc/gpio.h> #include <soc/gpio.h>
#include <variant/gpio.h> #include <variant/gpio.h>
#include <vendorcode/google/chromeos/chromeos.h> #include <vendorcode/google/chromeos/chromeos.h>

1
src/mainboard/intel/kblrvp/chromeos.c
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@ -17,7 +17,6 @@
#include <arch/io.h> #include <arch/io.h>
#include <device/device.h> #include <device/device.h>
#include <device/pci.h> #include <device/pci.h>
#include <rules.h>
#include <gpio.h> #include <gpio.h>
#include <soc/gpio.h> #include <soc/gpio.h>
#include <string.h> #include <string.h>

1
src/mainboard/intel/kunimitsu/chromeos.c
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@ -14,7 +14,6 @@
* GNU General Public License for more details. * GNU General Public License for more details.
*/ */
#include <rules.h>
#include <gpio.h> #include <gpio.h>
#include <soc/gpio.h> #include <soc/gpio.h>
#include <string.h> #include <string.h>

1
src/mainboard/intel/strago/chromeos.c
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@ -14,7 +14,6 @@
* GNU General Public License for more details. * GNU General Public License for more details.
*/ */
#include <rules.h>
#include <gpio.h> #include <gpio.h>
#include <string.h> #include <string.h>
#include <vendorcode/google/chromeos/chromeos.h> #include <vendorcode/google/chromeos/chromeos.h>

1
src/northbridge/intel/fsp_rangeley/northbridge.h
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@ -23,7 +23,6 @@
/* Everything below this line is ignored in the DSDT */ /* Everything below this line is ignored in the DSDT */
#ifndef __ACPI__ #ifndef __ACPI__
#include <rules.h>
#include <device/device.h> #include <device/device.h>
/* Device 0:0.0 PCI configuration space (Host Bridge) */ /* Device 0:0.0 PCI configuration space (Host Bridge) */

1
src/northbridge/intel/gm45/gm45.h
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@ -21,7 +21,6 @@
#ifndef __ACPI__ #ifndef __ACPI__
#include <rules.h>
#include <stdint.h> #include <stdint.h>
typedef enum { typedef enum {

1
src/northbridge/intel/sandybridge/sandybridge.h
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@ -65,7 +65,6 @@ enum platform_type {
PLATFORM_DESKTOP_SERVER, PLATFORM_DESKTOP_SERVER,
}; };
#include <rules.h>
/* Device 0:0.0 PCI configuration space (Host Bridge) */ /* Device 0:0.0 PCI configuration space (Host Bridge) */

1
src/security/vboot/bootmode.c
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@ -17,7 +17,6 @@
#include <bootmode.h> #include <bootmode.h>
#include <bootstate.h> #include <bootstate.h>
#include <cbmem.h> #include <cbmem.h>
#include <rules.h>
#include <string.h> #include <string.h>
#include <vb2_api.h> #include <vb2_api.h>
#include <security/vboot/misc.h> #include <security/vboot/misc.h>

1
src/security/vboot/vboot_common.c
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@ -20,7 +20,6 @@
#include <fmap.h> #include <fmap.h>
#include <gbb_header.h> #include <gbb_header.h>
#include <reset.h> #include <reset.h>
#include <rules.h>
#include <stddef.h> #include <stddef.h>
#include <string.h> #include <string.h>
#include <security/vboot/gbb.h> #include <security/vboot/gbb.h>

1
src/security/vboot/vboot_loader.c
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@ -18,7 +18,6 @@
#include <console/console.h> #include <console/console.h>
#include <ec/google/chromeec/ec.h> #include <ec/google/chromeec/ec.h>
#include <rmodule.h> #include <rmodule.h>
#include <rules.h>
#include <string.h> #include <string.h>
#include <security/vboot/misc.h> #include <security/vboot/misc.h>
#include <security/vboot/symbols.h> #include <security/vboot/symbols.h>

1
src/soc/amd/common/block/pi/agesawrapper.c
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@ -20,7 +20,6 @@
#include <cbfs.h> #include <cbfs.h>
#include <cbmem.h> #include <cbmem.h>
#include <delay.h> #include <delay.h>
#include <rules.h>
#include <rmodule.h> #include <rmodule.h>
#include <stage_cache.h> #include <stage_cache.h>
#include <string.h> #include <string.h>

1
src/soc/amd/stoneyridge/include/soc/pci_devs.h
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@ -17,7 +17,6 @@
#define __PI_STONEYRIDGE_PCI_DEVS_H__ #define __PI_STONEYRIDGE_PCI_DEVS_H__
#include <device/pci_def.h> #include <device/pci_def.h>
#include <rules.h>
#if !defined(__SIMPLE_DEVICE__) #if !defined(__SIMPLE_DEVICE__)
#include <device/device.h> #include <device/device.h>

1
src/soc/amd/stoneyridge/include/soc/southbridge.h
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@ -23,7 +23,6 @@
#include <device/pci_def.h> #include <device/pci_def.h>
#include <soc/iomap.h> #include <soc/iomap.h>
#include "chip.h" #include "chip.h"
#include <rules.h>
/* /*
* AcpiMmio Region * AcpiMmio Region

1
src/soc/intel/apollolake/include/soc/pci_devs.h
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@ -16,7 +16,6 @@
#define _SOC_APOLLOLAKE_PCI_DEVS_H_ #define _SOC_APOLLOLAKE_PCI_DEVS_H_
#include <device/pci_def.h> #include <device/pci_def.h>
#include <rules.h>
#define _SA_DEVFN(slot) PCI_DEVFN(SA_DEV_SLOT_ ## slot, 0) #define _SA_DEVFN(slot) PCI_DEVFN(SA_DEV_SLOT_ ## slot, 0)
#define _PCH_DEVFN(slot, func) PCI_DEVFN(PCH_DEV_SLOT_ ## slot, func) #define _PCH_DEVFN(slot, func) PCI_DEVFN(PCH_DEV_SLOT_ ## slot, func)

1
src/soc/intel/apollolake/pmutil.c
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@ -29,7 +29,6 @@
#include <intelblocks/pmclib.h> #include <intelblocks/pmclib.h>
#include <intelblocks/rtc.h> #include <intelblocks/rtc.h>
#include <intelblocks/tco.h> #include <intelblocks/tco.h>
#include <rules.h>
#include <soc/iomap.h> #include <soc/iomap.h>
#include <soc/cpu.h> #include <soc/cpu.h>
#include <soc/pci_devs.h> #include <soc/pci_devs.h>

1
src/soc/intel/braswell/acpi.c
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@ -30,7 +30,6 @@
#include <device/pci.h> #include <device/pci.h>
#include <ec/google/chromeec/ec.h> #include <ec/google/chromeec/ec.h>
#include <drivers/intel/gma/opregion.h> #include <drivers/intel/gma/opregion.h>
#include <rules.h>
#include <soc/acpi.h> #include <soc/acpi.h>
#include <soc/gfx.h> #include <soc/gfx.h>
#include <soc/iomap.h> #include <soc/iomap.h>

1
src/soc/intel/braswell/include/soc/iosf.h
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@ -17,7 +17,6 @@
#ifndef _SOC_IOSF_H_ #ifndef _SOC_IOSF_H_
#define _SOC_IOSF_H_ #define _SOC_IOSF_H_
#include <rules.h>
#include <stdint.h> #include <stdint.h>
#if ENV_RAMSTAGE #if ENV_RAMSTAGE
#include <device/device.h> #include <device/device.h>

1
src/soc/intel/braswell/include/soc/nvs.h
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@ -19,7 +19,6 @@
#define _SOC_NVS_H_ #define _SOC_NVS_H_
#include <commonlib/helpers.h> #include <commonlib/helpers.h>
#include <rules.h>
#include <soc/device_nvs.h> #include <soc/device_nvs.h>
#include <vendorcode/google/chromeos/gnvs.h> #include <vendorcode/google/chromeos/gnvs.h>

1
src/soc/intel/braswell/include/soc/smm.h
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@ -17,7 +17,6 @@
#ifndef _SOC_SMM_H_ #ifndef _SOC_SMM_H_
#define _SOC_SMM_H_ #define _SOC_SMM_H_
#include <rules.h>
#if ENV_RAMSTAGE #if ENV_RAMSTAGE
#include <stdint.h> #include <stdint.h>

1
src/soc/intel/braswell/pmutil.c
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@ -18,7 +18,6 @@
#include <arch/io.h> #include <arch/io.h>
#include <cbmem.h> #include <cbmem.h>
#include <console/console.h> #include <console/console.h>
#include <rules.h>
#include <soc/iomap.h> #include <soc/iomap.h>
#include <soc/lpc.h> #include <soc/lpc.h>
#include <soc/pci_devs.h> #include <soc/pci_devs.h>

1
src/soc/intel/braswell/spi.c
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@ -19,7 +19,6 @@
#include <commonlib/helpers.h> #include <commonlib/helpers.h>
#include <console/console.h> #include <console/console.h>
#include <delay.h> #include <delay.h>
#include <rules.h>
#include <soc/lpc.h> #include <soc/lpc.h>
#include <soc/pci_devs.h> #include <soc/pci_devs.h>
#include <spi_flash.h> #include <spi_flash.h>

1
src/soc/intel/braswell/tsc_freq.c
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@ -16,7 +16,6 @@
#include <cpu/x86/msr.h> #include <cpu/x86/msr.h>
#include <cpu/x86/tsc.h> #include <cpu/x86/tsc.h>
#include <rules.h>
#include <soc/msr.h> #include <soc/msr.h>
#if ENV_RAMSTAGE #if ENV_RAMSTAGE
#include <soc/ramstage.h> #include <soc/ramstage.h>

1
src/soc/intel/cannonlake/include/soc/pci_devs.h
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@ -18,7 +18,6 @@
#define _SOC_CANNONLAKE_PCI_DEVS_H_ #define _SOC_CANNONLAKE_PCI_DEVS_H_
#include <device/pci_def.h> #include <device/pci_def.h>
#include <rules.h>
#define _SA_DEVFN(slot) PCI_DEVFN(SA_DEV_SLOT_ ## slot, 0) #define _SA_DEVFN(slot) PCI_DEVFN(SA_DEV_SLOT_ ## slot, 0)
#define _PCH_DEVFN(slot, func) PCI_DEVFN(PCH_DEV_SLOT_ ## slot, func) #define _PCH_DEVFN(slot, func) PCI_DEVFN(PCH_DEV_SLOT_ ## slot, func)

1
src/soc/intel/cannonlake/pmutil.c
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@ -31,7 +31,6 @@
#include <intelblocks/rtc.h> #include <intelblocks/rtc.h>
#include <intelblocks/tco.h> #include <intelblocks/tco.h>
#include <halt.h> #include <halt.h>
#include <rules.h>
#include <stdlib.h> #include <stdlib.h>
#include <soc/gpe.h> #include <soc/gpe.h>
#include <soc/gpio.h> #include <soc/gpio.h>

1
src/soc/intel/common/block/p2sb/p2sb.c
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@ -20,7 +20,6 @@
#include <device/pci.h> #include <device/pci.h>
#include <device/pci_ids.h> #include <device/pci_ids.h>
#include <intelblocks/p2sb.h> #include <intelblocks/p2sb.h>
#include <rules.h>
#include <soc/iomap.h> #include <soc/iomap.h>
#include <soc/p2sb.h> #include <soc/p2sb.h>
#include <soc/pci_devs.h> #include <soc/pci_devs.h>

1
src/soc/intel/denverton_ns/include/soc/pci_devs.h
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@ -20,7 +20,6 @@
/* All these devices live on bus 0 with the associated device and function */ /* All these devices live on bus 0 with the associated device and function */
#include <rules.h>
#define _SA_DEVFN(slot) PCI_DEVFN(SA_DEV_SLOT_##slot, 0) #define _SA_DEVFN(slot) PCI_DEVFN(SA_DEV_SLOT_##slot, 0)
#define _PCH_DEVFN(slot, func) PCI_DEVFN(PCH_DEV_SLOT_##slot, func) #define _PCH_DEVFN(slot, func) PCI_DEVFN(PCH_DEV_SLOT_##slot, func)

1
src/soc/intel/icelake/include/soc/pci_devs.h
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@ -17,7 +17,6 @@
#define _SOC_ICELAKE_PCI_DEVS_H_ #define _SOC_ICELAKE_PCI_DEVS_H_
#include <device/pci_def.h> #include <device/pci_def.h>
#include <rules.h>
#define _SA_DEVFN(slot) PCI_DEVFN(SA_DEV_SLOT_ ## slot, 0) #define _SA_DEVFN(slot) PCI_DEVFN(SA_DEV_SLOT_ ## slot, 0)
#define _PCH_DEVFN(slot, func) PCI_DEVFN(PCH_DEV_SLOT_ ## slot, func) #define _PCH_DEVFN(slot, func) PCI_DEVFN(PCH_DEV_SLOT_ ## slot, func)

1
src/soc/intel/icelake/pmutil.c
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@ -30,7 +30,6 @@
#include <intelblocks/rtc.h> #include <intelblocks/rtc.h>
#include <intelblocks/tco.h> #include <intelblocks/tco.h>
#include <halt.h> #include <halt.h>
#include <rules.h>
#include <stdlib.h> #include <stdlib.h>
#include <soc/gpe.h> #include <soc/gpe.h>
#include <soc/gpio.h> #include <soc/gpio.h>

1
src/soc/intel/skylake/include/soc/nvs.h
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@ -19,7 +19,6 @@
#define _SOC_NVS_H_ #define _SOC_NVS_H_
#include <commonlib/helpers.h> #include <commonlib/helpers.h>
#include <rules.h>
#include <vendorcode/google/chromeos/gnvs.h> #include <vendorcode/google/chromeos/gnvs.h>
typedef struct global_nvs_t { typedef struct global_nvs_t {

1
src/soc/intel/skylake/include/soc/pch.h
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@ -19,7 +19,6 @@
#define _SOC_PCH_H_ #define _SOC_PCH_H_
#include <device/device.h> #include <device/device.h>
#include <rules.h>
void pch_log_state(void); void pch_log_state(void);
#if ENV_RAMSTAGE #if ENV_RAMSTAGE

1
src/soc/intel/skylake/include/soc/pci_devs.h
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@ -18,7 +18,6 @@
#define _SOC_SKYLAKE_PCI_DEVS_H_ #define _SOC_SKYLAKE_PCI_DEVS_H_
#include <device/pci_def.h> #include <device/pci_def.h>
#include <rules.h>
#define _SA_DEVFN(slot) PCI_DEVFN(SA_DEV_SLOT_ ## slot, 0) #define _SA_DEVFN(slot) PCI_DEVFN(SA_DEV_SLOT_ ## slot, 0)
#define _PCH_DEVFN(slot, func) PCI_DEVFN(PCH_DEV_SLOT_ ## slot, func) #define _PCH_DEVFN(slot, func) PCI_DEVFN(PCH_DEV_SLOT_ ## slot, func)

1
src/soc/intel/skylake/pmutil.c
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@ -29,7 +29,6 @@
#include <halt.h> #include <halt.h>
#include <intelblocks/lpc_lib.h> #include <intelblocks/lpc_lib.h>
#include <intelblocks/tco.h> #include <intelblocks/tco.h>
#include <rules.h>
#include <stdlib.h> #include <stdlib.h>
#include <soc/gpe.h> #include <soc/gpe.h>
#include <soc/gpio.h> #include <soc/gpio.h>

1
src/southbridge/amd/rs780/rs780.h
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@ -16,7 +16,6 @@
#ifndef __RS780_H__ #ifndef __RS780_H__
#define __RS780_H__ #define __RS780_H__
#include <rules.h>
#include <stdint.h> #include <stdint.h>
#include "chip.h" #include "chip.h"
#include "rev.h" #include "rev.h"

1
src/southbridge/intel/bd82x6x/early_pch_common.c
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@ -20,7 +20,6 @@
#include "pch.h" #include "pch.h"
#include <arch/acpi.h> #include <arch/acpi.h>
#include <console/console.h> #include <console/console.h>
#include <rules.h>
#if ENV_ROMSTAGE #if ENV_ROMSTAGE
int southbridge_detect_s3_resume(void) int southbridge_detect_s3_resume(void)