buildsystem: Promote rules.h to default include

Does not fix 3rdparty/, *.S or *.ld or yet.

Change-Id: I66b48013dd89540b35ab219d2b64bc13f5f19cda
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/17656
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>

Makefile.inc

@@ -383,6 +383,7 @@ CPPFLAGS_common += -Isrc/device/oprom/include
 VBOOT_SOURCE ?= 3rdparty/vboot
 CPPFLAGS_common += -I$(VBOOT_SOURCE)/firmware/include
 CPPFLAGS_common += -include $(src)/include/kconfig.h
+CPPFLAGS_common += -include $(src)/include/rules.h
 CPPFLAGS_common += -include $(src)/commonlib/include/commonlib/compiler.h
 CPPFLAGS_common += -I3rdparty
 CPPFLAGS_common += -D__BUILD_DIR__=\"$(obj)\"

src/arch/arm64/boot.c

@@ -19,7 +19,6 @@
 #include <arch/transition.h>
 #include <arm_tf.h>
 #include <program_loading.h>
-#include <rules.h>
 #include <string.h>
 
 static void run_payload(struct prog *prog)

src/arch/riscv/boot.c

@@ -17,7 +17,6 @@
 #include <vm.h>
 #include <arch/boot.h>
 #include <arch/encoding.h>
-#include <rules.h>
 #include <console/console.h>
 #include <arch/smp/smp.h>
 

src/arch/riscv/stages.c

@@ -28,7 +28,6 @@
 #include <arch/encoding.h>
 #include <arch/stages.h>
 #include <arch/smp/smp.h>
-#include <rules.h>
 
 void stage_entry(void)
 {

src/arch/x86/acpi_s3.c

@@ -22,7 +22,6 @@
 #include <timestamp.h>
 #include <program_loading.h>
 #include <romstage_handoff.h>
-#include <rules.h>
 #include <symbols.h>
 
 #if ENV_RAMSTAGE || ENV_POSTCAR

src/arch/x86/exception.c

@@ -19,7 +19,6 @@
 #include <console/streams.h>
 #include <cpu/x86/cr.h>
 #include <cpu/x86/lapic.h>
-#include <rules.h>
 #include <stdint.h>
 #include <string.h>
 

src/arch/x86/include/arch/acpi.h

@@ -57,7 +57,6 @@
 
 #if !defined(__ASSEMBLER__) && !defined(__ACPI__) && !defined(__ROMCC__)
 #include <stdint.h>
-#include <rules.h>
 #include <commonlib/helpers.h>
 #include <device/device.h>
 #include <uuid.h>

src/arch/x86/include/arch/cpu.h

@@ -16,7 +16,6 @@
 
 #include <stdint.h>
 #include <stddef.h>
-#include <rules.h>
 
 /*
  * EFLAGS bits

src/arch/x86/include/arch/early_variables.h

@@ -18,7 +18,6 @@
 
 #include <arch/symbols.h>
 #include <stdlib.h>
-#include <rules.h>
 
 #if ENV_CACHE_AS_RAM && !IS_ENABLED(CONFIG_NO_CAR_GLOBAL_MIGRATION)
 asm(".section .car.global_data,\"w\",@nobits");

src/arch/x86/include/arch/exception.h

@@ -31,7 +31,6 @@
 #define _ARCH_EXCEPTION_H
 
 #include <arch/cpu.h>
-#include <rules.h>
 
 #if IS_ENABLED(CONFIG_IDT_IN_EVERY_STAGE) || ENV_RAMSTAGE
 asmlinkage void exception_init(void);

src/arch/x86/include/arch/io.h

@@ -16,7 +16,6 @@
 
 #include <endian.h>
 #include <stdint.h>
-#include <rules.h>
 #include <device/pci_type.h>
 
 /*

src/arch/x86/include/arch/memlayout.h

@@ -16,7 +16,6 @@
 #ifndef __ARCH_MEMLAYOUT_H
 #define __ARCH_MEMLAYOUT_H
 
-#include <rules.h>
 
 #if ENV_BOOTBLOCK || ENV_ROMSTAGE || ENV_VERSTAGE
 /* No .data or .bss sections. Cache as RAM is handled separately. */

src/arch/x86/rdrand.c

@@ -14,7 +14,6 @@
  */
 
 #include <random.h>
-#include <rules.h>
 
 /*
  * Intel recommends that applications attempt 10 retries in a tight loop

src/commonlib/storage/pci_sdhci.c

@@ -13,7 +13,6 @@
  * GNU General Public License for more details.
  */
 
-#include <rules.h>
 #if ENV_RAMSTAGE
 #define __SIMPLE_DEVICE__		1
 #endif

src/console/console.c

@@ -22,7 +22,6 @@
 #include <console/usb.h>
 #include <console/spi.h>
 #include <console/flash.h>
-#include <rules.h>
 
 void console_hw_init(void)
 {

src/console/init.c

@@ -20,7 +20,6 @@
 #include <console/streams.h>
 #include <device/pci.h>
 #include <option.h>
-#include <rules.h>
 #include <version.h>
 
 /* Mutable console log level only allowed when RAM comes online. */

src/console/post.c

@@ -20,7 +20,6 @@
 #include <device/device.h>
 #include <pc80/mc146818rtc.h>
 #include <smp/spinlock.h>
-#include <rules.h>
 
 /* Write POST information */
 

src/cpu/intel/microcode/microcode.c

@@ -27,7 +27,6 @@
 #include <arch/cpu.h>
 #include <cpu/x86/msr.h>
 #include <cpu/intel/microcode.h>
-#include <rules.h>
 
 #if !defined(__PRE_RAM__)
 #include <smp/spinlock.h>

src/cpu/x86/32bit/entry32.inc

@@ -15,7 +15,6 @@
 
 #include <arch/rom_segs.h>
 #include <cpu/x86/post_code.h>
-#include <rules.h>
 #include <arch/x86/gdt_init.S>
 
 	.code32

src/cpu/x86/pae/pgtbl.c

@@ -20,7 +20,6 @@
 #include <cpu/x86/cr.h>
 #include <cpu/x86/msr.h>
 #include <cpu/x86/pae.h>
-#include <rules.h>
 #include <string.h>
 #include <symbols.h>
 

src/drivers/intel/fsp1_1/cache_as_ram.inc

@@ -24,7 +24,6 @@
  * performs the final stage of initialization.
  */
 
-#include <rules.h>
 
 #define LHLT_DELAY	0x50000		/* I/O delay between post codes on failure */
 

src/drivers/intel/fsp1_1/include/fsp/util.h

@@ -17,7 +17,6 @@
 #ifndef FSP1_1_UTIL_H
 #define FSP1_1_UTIL_H
 
-#include <rules.h>
 #include <fsp/api.h>
 /* Current users expect to get the SoC's FSP definitions by including util.h. */
 #include <fsp/soc_binding.h>

src/drivers/intel/fsp2_0/include/fsp/info_header.h

@@ -13,7 +13,6 @@
 #ifndef _FSP2_0_INFO_HEADER_H_
 #define _FSP2_0_INFO_HEADER_H_
 
-#include <rules.h>
 #include <stdint.h>
 #include <stdlib.h>
 #include <types.h>

src/drivers/net/ne2k.c

@@ -34,7 +34,6 @@ SMC8416 PIO support added by Andrew Bettison (andrewb@zip.com.au) on 4/3/02
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <device/pci_ops.h>
-#include <rules.h>
 #include <stdlib.h>
 #include <string.h>
 #include <ip_checksum.h>

src/drivers/spi/spi_flash.c

@@ -12,7 +12,6 @@
 #include <boot_device.h>
 #include <cpu/x86/smm.h>
 #include <delay.h>
-#include <rules.h>
 #include <stdlib.h>
 #include <string.h>
 #include <spi-generic.h>

src/drivers/uart/uart8250io.c

@@ -14,7 +14,6 @@
  * GNU General Public License for more details.
  */
 
-#include <rules.h>
 #include <stdlib.h>
 #include <arch/io.h>
 #include <boot/coreboot_tables.h>

src/drivers/uart/uart8250mem.c

@@ -19,7 +19,6 @@
 #include <console/uart.h>
 #include <device/device.h>
 #include <delay.h>
-#include <rules.h>
 #include <stdint.h>
 #include "uart8250reg.h"
 

src/include/bootstate.h

@@ -15,7 +15,6 @@
 #ifndef BOOTSTATE_H
 #define BOOTSTATE_H
 
-#include <rules.h>
 #include <string.h>
 #include <stdlib.h>
 #include <stddef.h>

src/include/cbmem.h

@@ -18,7 +18,6 @@
 #define _CBMEM_H_
 
 #include <commonlib/cbmem_id.h>
-#include <rules.h>
 #include <stddef.h>
 #include <stdint.h>
 #include <boot/coreboot_tables.h>

src/include/console/cbmem_console.h

@@ -15,7 +15,6 @@
 #ifndef _CONSOLE_CBMEM_CONSOLE_H_
 #define _CONSOLE_CBMEM_CONSOLE_H_
 
-#include <rules.h>
 #include <stdint.h>
 
 void cbmemc_init(void);

src/include/console/console.h

@@ -17,7 +17,6 @@
 #define CONSOLE_CONSOLE_H_
 
 #include <stdint.h>
-#include <rules.h>
 #include <arch/cpu.h>
 #include <console/post_codes.h>
 #include <commonlib/loglevel.h>

src/include/console/flash.h

@@ -16,7 +16,6 @@
 #ifndef CONSOLE_FLASH_H
 #define CONSOLE_FLASH_H 1
 
-#include <rules.h>
 #include <stdint.h>
 
 void flashconsole_init(void);

src/include/console/ne2k.h

@@ -16,7 +16,6 @@
 #ifndef _NE2K_H__
 #define _NE2K_H__
 
-#include <rules.h>
 #include <stdint.h>
 
 void ne2k_append_data(unsigned char *d, int len, unsigned int base);

src/include/console/qemu_debugcon.h

@@ -1,7 +1,6 @@
 #ifndef _QEMU_DEBUGCON_H_
 #define _QEMU_DEBUGCON_H_
 
-#include <rules.h>
 #include <stdint.h>
 
 void qemu_debugcon_init(void);

src/include/console/spi.h

@@ -16,7 +16,6 @@
 #ifndef CONSOLE_SPI_H
 #define CONSOLE_SPI_H 1
 
-#include <rules.h>
 #include <stdint.h>
 
 void spiconsole_init(void);

src/include/console/spkmodem.h

@@ -1,7 +1,6 @@
 #ifndef SPKMODEM_H
 #define SPKMODEM_H 1
 
-#include <rules.h>
 #include <stdint.h>
 
 void spkmodem_init(void);

src/include/console/uart.h

@@ -16,7 +16,6 @@
 #ifndef CONSOLE_UART_H
 #define CONSOLE_UART_H
 
-#include <rules.h>
 #include <stdint.h>
 
 /* Return the clock frequency UART uses as reference clock for

src/include/console/usb.h

@@ -17,7 +17,6 @@
 #ifndef _CONSOLE_USB_H_
 #define _CONSOLE_USB_H_
 
-#include <rules.h>
 #include <stdint.h>
 
 void usbdebug_init(void);

src/include/device/device.h

@@ -11,7 +11,6 @@
 
 #include <stdint.h>
 #include <stddef.h>
-#include <rules.h>
 #include <device/resource.h>
 #include <device/path.h>
 #include <device/pci_type.h>

src/include/device/pci.h

@@ -19,7 +19,6 @@
 
 #include <stdint.h>
 #include <stddef.h>
-#include <rules.h>
 #include <arch/io.h>
 #include <device/pci_def.h>
 #include <device/resource.h>

src/include/device/pnp.h

@@ -2,7 +2,6 @@
 #define DEVICE_PNP_H
 
 #include <stdint.h>
-#include <rules.h>
 #include <device/device.h>
 #include <device/pnp_def.h>
 #include <arch/io.h>

src/include/memlayout.h

@@ -18,7 +18,6 @@
 #ifndef __MEMLAYOUT_H
 #define __MEMLAYOUT_H
 
-#include <rules.h>
 #include <arch/memlayout.h>
 
 /* Macros that the architecture can override. */

src/include/stddef.h

@@ -2,7 +2,6 @@
 #define STDDEF_H
 
 #include <commonlib/helpers.h>
-#include <rules.h>
 
 typedef long ptrdiff_t;
 #ifndef __SIZE_TYPE__

src/lib/bootmode.c

@@ -13,7 +13,6 @@
  * GNU General Public License for more details.
  */
 
-#include <rules.h>
 #include <bootmode.h>
 #include <vendorcode/google/chromeos/chromeos.h>
 

src/lib/cbmem_common.c

@@ -15,7 +15,6 @@
 
 #include <cbmem.h>
 #include <bootstate.h>
-#include <rules.h>
 #include <symbols.h>
 
 void cbmem_run_init_hooks(int is_recovery)

src/lib/ext_stage_cache.c

@@ -18,7 +18,6 @@
 #include <cbmem.h>
 #include <console/console.h>
 #include <imd.h>
-#include <rules.h>
 #include <stage_cache.h>
 #include <string.h>
 

src/lib/imd_cbmem.c

@@ -18,7 +18,6 @@
 #include <console/console.h>
 #include <cbmem.h>
 #include <imd.h>
-#include <rules.h>
 #include <string.h>
 #include <stdlib.h>
 #include <arch/early_variables.h>

src/lib/prog_loaders.c

@@ -25,7 +25,6 @@
 #include <reset.h>
 #include <romstage_handoff.h>
 #include <rmodule.h>
-#include <rules.h>
 #include <stage_cache.h>
 #include <symbols.h>
 #include <timestamp.h>

src/lib/romstage_handoff.c

@@ -18,7 +18,6 @@
 #include <cbmem.h>
 #include <console/console.h>
 #include <romstage_handoff.h>
-#include <rules.h>
 
 struct romstage_handoff {
 	/* Indicate if the current boot is an S3 resume. If

src/lib/timestamp.c

@@ -23,7 +23,6 @@
 #include <timer.h>
 #include <timestamp.h>
 #include <arch/early_variables.h>
-#include <rules.h>
 #include <smp/node.h>
 
 #define MAX_TIMESTAMPS 192

src/mainboard/google/cyan/chromeos.c

@@ -15,7 +15,6 @@
  */
 
 #include <arch/io.h>
-#include <rules.h>
 #include <gpio.h>
 #include <soc/gpio.h>
 #include <string.h>

src/mainboard/google/dragonegg/chromeos.c

@@ -16,7 +16,6 @@
 #include <arch/acpi.h>
 #include <baseboard/variants.h>
 #include <gpio.h>
-#include <rules.h>
 #include <soc/gpio.h>
 #include <vendorcode/google/chromeos/chromeos.h>
 

src/mainboard/google/eve/chromeos.c

@@ -14,7 +14,6 @@
  * GNU General Public License for more details.
  */
 
-#include <rules.h>
 #include <gpio.h>
 #include <soc/gpio.h>
 #include <vendorcode/google/chromeos/chromeos.h>

src/mainboard/google/fizz/chromeos.c

@@ -14,7 +14,6 @@
  */
 
 #include <gpio.h>
-#include <rules.h>
 #include <baseboard/variants.h>
 #include <soc/gpio.h>
 #include <vendorcode/google/chromeos/chromeos.h>

src/mainboard/google/glados/chromeos.c

@@ -14,7 +14,6 @@
  * GNU General Public License for more details.
  */
 
-#include <rules.h>
 #include <gpio.h>
 #include <soc/gpio.h>
 #include <string.h>

src/mainboard/google/kahlee/ec.c

@@ -16,7 +16,6 @@
 #include <arch/acpi.h>
 #include <console/console.h>
 #include <ec/google/chromeec/ec.h>
-#include <rules.h>
 #include <soc/southbridge.h>
 #include <variant/ec.h>
 

src/mainboard/google/octopus/ec.c

@@ -19,7 +19,6 @@
 #include <ec/ec.h>
 #include <ec/google/chromeec/ec.h>
 #include <intelblocks/lpc_lib.h>
-#include <rules.h>
 #include <variant/ec.h>
 
 static void ramstage_ec_init(void)

src/mainboard/google/poppy/chromeos.c

@@ -16,7 +16,6 @@
 #include <arch/acpi.h>
 #include <baseboard/variants.h>
 #include <gpio.h>
-#include <rules.h>
 #include <soc/gpio.h>
 #include <vendorcode/google/chromeos/chromeos.h>
 

src/mainboard/google/reef/ec.c

@@ -18,7 +18,6 @@
 #include <ec/ec.h>
 #include <ec/google/chromeec/ec.h>
 #include <intelblocks/lpc_lib.h>
-#include <rules.h>
 #include <variant/ec.h>
 
 static void ramstage_ec_init(void)

src/mainboard/google/sarien/chromeos.c

@@ -16,7 +16,6 @@
 #include <arch/acpi.h>
 #include <boot/coreboot_tables.h>
 #include <gpio.h>
-#include <rules.h>
 #include <soc/gpio.h>
 #include <variant/gpio.h>
 #include <vendorcode/google/chromeos/chromeos.h>

src/mainboard/google/storm/mmu.c

@@ -11,7 +11,6 @@
  */
 
 #include <arch/cache.h>
-#include <rules.h>
 #include <soc/soc_services.h>
 #include <symbols.h>
 #include "mmu.h"

src/mainboard/intel/cannonlake_rvp/chromeos.c

@@ -16,7 +16,6 @@
 #include <arch/acpi.h>
 #include <baseboard/variants.h>
 #include <gpio.h>
-#include <rules.h>
 #include <soc/gpio.h>
 #include <variant/gpio.h>
 #include <vendorcode/google/chromeos/chromeos.h>

src/mainboard/intel/coffeelake_rvp/chromeos.c

@@ -16,7 +16,6 @@
 #include <arch/acpi.h>
 #include <baseboard/variants.h>
 #include <gpio.h>
-#include <rules.h>
 #include <soc/gpio.h>
 #include <vendorcode/google/chromeos/chromeos.h>
 

src/mainboard/intel/glkrvp/ec.c

@@ -19,7 +19,6 @@
 #include <ec/ec.h>
 #include <ec/google/chromeec/ec.h>
 #include <intelblocks/lpc_lib.h>
-#include <rules.h>
 #include <variant/ec.h>
 
 static void ramstage_ec_init(void)

src/mainboard/intel/icelake_rvp/chromeos.c

@@ -16,7 +16,6 @@
 #include <arch/acpi.h>
 #include <baseboard/variants.h>
 #include <gpio.h>
-#include <rules.h>
 #include <soc/gpio.h>
 #include <variant/gpio.h>
 #include <vendorcode/google/chromeos/chromeos.h>

src/mainboard/intel/kblrvp/chromeos.c

@@ -17,7 +17,6 @@
 #include <arch/io.h>
 #include <device/device.h>
 #include <device/pci.h>
-#include <rules.h>
 #include <gpio.h>
 #include <soc/gpio.h>
 #include <string.h>

src/mainboard/intel/kunimitsu/chromeos.c

@@ -14,7 +14,6 @@
  * GNU General Public License for more details.
  */
 
-#include <rules.h>
 #include <gpio.h>
 #include <soc/gpio.h>
 #include <string.h>

src/mainboard/intel/strago/chromeos.c

@@ -14,7 +14,6 @@
  * GNU General Public License for more details.
  */
 
-#include <rules.h>
 #include <gpio.h>
 #include <string.h>
 #include <vendorcode/google/chromeos/chromeos.h>

src/northbridge/intel/fsp_rangeley/northbridge.h

@@ -23,7 +23,6 @@
 /* Everything below this line is ignored in the DSDT */
 #ifndef __ACPI__
 
-#include <rules.h>
 #include <device/device.h>
 
 /* Device 0:0.0 PCI configuration space (Host Bridge) */

src/northbridge/intel/gm45/gm45.h

@@ -21,7 +21,6 @@
 
 #ifndef __ACPI__
 
-#include <rules.h>
 #include <stdint.h>
 
 typedef enum {

src/northbridge/intel/sandybridge/sandybridge.h

@@ -65,7 +65,6 @@ enum platform_type {
 	PLATFORM_DESKTOP_SERVER,
 };
 
-#include <rules.h>
 
 /* Device 0:0.0 PCI configuration space (Host Bridge) */
 

src/security/vboot/bootmode.c

@@ -17,7 +17,6 @@
 #include <bootmode.h>
 #include <bootstate.h>
 #include <cbmem.h>
-#include <rules.h>
 #include <string.h>
 #include <vb2_api.h>
 #include <security/vboot/misc.h>

src/security/vboot/vboot_common.c

@@ -20,7 +20,6 @@
 #include <fmap.h>
 #include <gbb_header.h>
 #include <reset.h>
-#include <rules.h>
 #include <stddef.h>
 #include <string.h>
 #include <security/vboot/gbb.h>

src/security/vboot/vboot_loader.c

@@ -18,7 +18,6 @@
 #include <console/console.h>
 #include <ec/google/chromeec/ec.h>
 #include <rmodule.h>
-#include <rules.h>
 #include <string.h>
 #include <security/vboot/misc.h>
 #include <security/vboot/symbols.h>

src/soc/amd/common/block/pi/agesawrapper.c

@@ -20,7 +20,6 @@
 #include <cbfs.h>
 #include <cbmem.h>
 #include <delay.h>
-#include <rules.h>
 #include <rmodule.h>
 #include <stage_cache.h>
 #include <string.h>

src/soc/amd/stoneyridge/include/soc/pci_devs.h

@@ -17,7 +17,6 @@
 #define __PI_STONEYRIDGE_PCI_DEVS_H__
 
 #include <device/pci_def.h>
-#include <rules.h>
 
 #if !defined(__SIMPLE_DEVICE__)
 #include <device/device.h>

src/soc/amd/stoneyridge/include/soc/southbridge.h

@@ -23,7 +23,6 @@
 #include <device/pci_def.h>
 #include <soc/iomap.h>
 #include "chip.h"
-#include <rules.h>
 
 /*
  * AcpiMmio Region

src/soc/intel/apollolake/include/soc/pci_devs.h

@@ -16,7 +16,6 @@
 #define _SOC_APOLLOLAKE_PCI_DEVS_H_
 
 #include <device/pci_def.h>
-#include <rules.h>
 
 #define _SA_DEVFN(slot)		PCI_DEVFN(SA_DEV_SLOT_ ## slot, 0)
 #define _PCH_DEVFN(slot, func)	PCI_DEVFN(PCH_DEV_SLOT_ ## slot, func)

src/soc/intel/apollolake/pmutil.c

@@ -29,7 +29,6 @@
 #include <intelblocks/pmclib.h>
 #include <intelblocks/rtc.h>
 #include <intelblocks/tco.h>
-#include <rules.h>
 #include <soc/iomap.h>
 #include <soc/cpu.h>
 #include <soc/pci_devs.h>

src/soc/intel/braswell/acpi.c

@@ -30,7 +30,6 @@
 #include <device/pci.h>
 #include <ec/google/chromeec/ec.h>
 #include <drivers/intel/gma/opregion.h>
-#include <rules.h>
 #include <soc/acpi.h>
 #include <soc/gfx.h>
 #include <soc/iomap.h>

src/soc/intel/braswell/include/soc/iosf.h

@@ -17,7 +17,6 @@
 #ifndef _SOC_IOSF_H_
 #define _SOC_IOSF_H_
 
-#include <rules.h>
 #include <stdint.h>
 #if ENV_RAMSTAGE
 #include <device/device.h>

src/soc/intel/braswell/include/soc/nvs.h

@@ -19,7 +19,6 @@
 #define _SOC_NVS_H_
 
 #include <commonlib/helpers.h>
-#include <rules.h>
 #include <soc/device_nvs.h>
 #include <vendorcode/google/chromeos/gnvs.h>
 

src/soc/intel/braswell/include/soc/smm.h

@@ -17,7 +17,6 @@
 #ifndef _SOC_SMM_H_
 #define _SOC_SMM_H_
 
-#include <rules.h>
 
 #if ENV_RAMSTAGE
 #include <stdint.h>

src/soc/intel/braswell/pmutil.c

@@ -18,7 +18,6 @@
 #include <arch/io.h>
 #include <cbmem.h>
 #include <console/console.h>
-#include <rules.h>
 #include <soc/iomap.h>
 #include <soc/lpc.h>
 #include <soc/pci_devs.h>

src/soc/intel/braswell/spi.c

@@ -19,7 +19,6 @@
 #include <commonlib/helpers.h>
 #include <console/console.h>
 #include <delay.h>
-#include <rules.h>
 #include <soc/lpc.h>
 #include <soc/pci_devs.h>
 #include <spi_flash.h>

src/soc/intel/braswell/tsc_freq.c

@@ -16,7 +16,6 @@
 
 #include <cpu/x86/msr.h>
 #include <cpu/x86/tsc.h>
-#include <rules.h>
 #include <soc/msr.h>
 #if ENV_RAMSTAGE
 #include <soc/ramstage.h>

src/soc/intel/cannonlake/include/soc/pci_devs.h

@@ -18,7 +18,6 @@
 #define _SOC_CANNONLAKE_PCI_DEVS_H_
 
 #include <device/pci_def.h>
-#include <rules.h>
 
 #define _SA_DEVFN(slot)		PCI_DEVFN(SA_DEV_SLOT_ ## slot, 0)
 #define _PCH_DEVFN(slot, func)	PCI_DEVFN(PCH_DEV_SLOT_ ## slot, func)

src/soc/intel/cannonlake/pmutil.c

@@ -31,7 +31,6 @@
 #include <intelblocks/rtc.h>
 #include <intelblocks/tco.h>
 #include <halt.h>
-#include <rules.h>
 #include <stdlib.h>
 #include <soc/gpe.h>
 #include <soc/gpio.h>

src/soc/intel/common/block/p2sb/p2sb.c

@@ -20,7 +20,6 @@
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <intelblocks/p2sb.h>
-#include <rules.h>
 #include <soc/iomap.h>
 #include <soc/p2sb.h>
 #include <soc/pci_devs.h>

src/soc/intel/denverton_ns/include/soc/pci_devs.h

@@ -20,7 +20,6 @@
 
 /* All these devices live on bus 0 with the associated device and function */
 
-#include <rules.h>
 
 #define _SA_DEVFN(slot) PCI_DEVFN(SA_DEV_SLOT_##slot, 0)
 #define _PCH_DEVFN(slot, func) PCI_DEVFN(PCH_DEV_SLOT_##slot, func)

src/soc/intel/icelake/include/soc/pci_devs.h

@@ -17,7 +17,6 @@
 #define _SOC_ICELAKE_PCI_DEVS_H_
 
 #include <device/pci_def.h>
-#include <rules.h>
 
 #define _SA_DEVFN(slot)		PCI_DEVFN(SA_DEV_SLOT_ ## slot, 0)
 #define _PCH_DEVFN(slot, func)	PCI_DEVFN(PCH_DEV_SLOT_ ## slot, func)

src/soc/intel/icelake/pmutil.c

@@ -30,7 +30,6 @@
 #include <intelblocks/rtc.h>
 #include <intelblocks/tco.h>
 #include <halt.h>
-#include <rules.h>
 #include <stdlib.h>
 #include <soc/gpe.h>
 #include <soc/gpio.h>

src/soc/intel/skylake/include/soc/nvs.h

@@ -19,7 +19,6 @@
 #define _SOC_NVS_H_
 
 #include <commonlib/helpers.h>
-#include <rules.h>
 #include <vendorcode/google/chromeos/gnvs.h>
 
 typedef struct global_nvs_t {

src/soc/intel/skylake/include/soc/pch.h

@@ -19,7 +19,6 @@
 #define _SOC_PCH_H_
 
 #include <device/device.h>
-#include <rules.h>
 
 void pch_log_state(void);
 #if ENV_RAMSTAGE

src/soc/intel/skylake/include/soc/pci_devs.h

@@ -18,7 +18,6 @@
 #define _SOC_SKYLAKE_PCI_DEVS_H_
 
 #include <device/pci_def.h>
-#include <rules.h>
 
 #define _SA_DEVFN(slot)		PCI_DEVFN(SA_DEV_SLOT_ ## slot, 0)
 #define _PCH_DEVFN(slot, func)	PCI_DEVFN(PCH_DEV_SLOT_ ## slot, func)

src/soc/intel/skylake/pmutil.c

@@ -29,7 +29,6 @@
 #include <halt.h>
 #include <intelblocks/lpc_lib.h>
 #include <intelblocks/tco.h>
-#include <rules.h>
 #include <stdlib.h>
 #include <soc/gpe.h>
 #include <soc/gpio.h>

src/southbridge/amd/rs780/rs780.h

@@ -16,7 +16,6 @@
 #ifndef __RS780_H__
 #define __RS780_H__
 
-#include <rules.h>
 #include <stdint.h>
 #include "chip.h"
 #include "rev.h"

src/southbridge/intel/bd82x6x/early_pch_common.c

@@ -20,7 +20,6 @@
 #include "pch.h"
 #include <arch/acpi.h>
 #include <console/console.h>
-#include <rules.h>
 
 #if ENV_ROMSTAGE
 int southbridge_detect_s3_resume(void)