Replace SERIAL_CPU_INIT with PARALLEL_CPU_INIT

Lines with 'select SERIAL_CPU_INIT' where redundant with the
default being yes. Since there is no 'unselect SERIAL_CPU_INIT'
possibility, invert the default and rename option.

This squelches Kconfig warnings about unmet dependencies.

Change-Id: Iae546c56006278489ebae10f2daa627af48abe94
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5700
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This commit is contained in:
Kyösti Mälkki 2014-05-08 15:27:15 +03:00
parent a7e2cc507b
commit 5c3f384f06
64 changed files with 37 additions and 146 deletions

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@ -37,16 +37,13 @@ config CPU_SPECIFIC_OPTIONS
select UDELAY_LAPIC
select SMM_TSEG
select SUPPORT_CPU_UCODE_IN_CBFS if HAVE_FSP_BIN
select PARALLEL_CPU_INIT
select TSC_SYNC_MFENCE
config BOOTBLOCK_CPU_INIT
string
default "cpu/intel/fsp_model_206ax/bootblock.c"
config SERIAL_CPU_INIT
bool
default n
config SMM_TSEG_SIZE
hex
default 0x800000

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@ -22,16 +22,13 @@ config CPU_SPECIFIC_OPTIONS
#select AP_IN_SIPI_WAIT
select TSC_SYNC_MFENCE
select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
select PARALLEL_CPU_INIT
select PARALLEL_MP
config BOOTBLOCK_CPU_INIT
string
default "cpu/intel/haswell/bootblock.c"
config SERIAL_CPU_INIT
bool
default n
config SMM_TSEG_SIZE
hex
default 0x800000

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@ -7,7 +7,7 @@
#include <smp/spinlock.h>
#include <assert.h>
#if !CONFIG_SERIAL_CPU_INIT
#if CONFIG_PARALLEL_CPU_INIT
#error Intel hyper-threading requires serialized cpu init
#endif

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@ -15,6 +15,7 @@ config CPU_SPECIFIC_OPTIONS
select TSC_CONSTANT_RATE
select SMM_TSEG
select SUPPORT_CPU_UCODE_IN_CBFS
select PARALLEL_CPU_INIT
#select AP_IN_SIPI_WAIT
select TSC_SYNC_MFENCE
@ -22,10 +23,6 @@ config BOOTBLOCK_CPU_INIT
string
default "cpu/intel/model_2065x/bootblock.c"
config SERIAL_CPU_INIT
bool
default n
config SMM_TSEG_SIZE
hex
default 0x800000

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@ -16,6 +16,7 @@ config CPU_SPECIFIC_OPTIONS
select UDELAY_LAPIC
select SMM_TSEG
select SUPPORT_CPU_UCODE_IN_CBFS
select PARALLEL_CPU_INIT
#select AP_IN_SIPI_WAIT
select TSC_SYNC_MFENCE
@ -23,10 +24,6 @@ config BOOTBLOCK_CPU_INIT
string
default "cpu/intel/model_206ax/bootblock.c"
config SERIAL_CPU_INIT
bool
default n
config SMM_TSEG_SIZE
hex
default 0x800000

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@ -1,6 +1,6 @@
config SERIAL_CPU_INIT
config PARALLEL_CPU_INIT
bool
default y
default n
config UDELAY_IO
bool

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@ -406,9 +406,9 @@ void stop_this_cpu(void)
void asmlinkage secondary_cpu_init(unsigned int index)
{
atomic_inc(&active_cpus);
#if CONFIG_SERIAL_CPU_INIT
spin_lock(&start_cpu_lock);
#endif
if (!IS_ENABLED(CONFIG_PARALLEL_CPU_INIT))
spin_lock(&start_cpu_lock);
#ifdef __SSE3__
/*
@ -421,9 +421,9 @@ void asmlinkage secondary_cpu_init(unsigned int index)
write_cr4(cr4_val);
#endif
cpu_initialize(index);
#if CONFIG_SERIAL_CPU_INIT
spin_unlock(&start_cpu_lock);
#endif
if (!IS_ENABLED(CONFIG_PARALLEL_CPU_INIT))
spin_unlock(&start_cpu_lock);
atomic_dec(&active_cpus);
@ -439,11 +439,9 @@ static void start_other_cpus(struct bus *cpu_bus, device_t bsp_cpu)
if (cpu->path.type != DEVICE_PATH_APIC) {
continue;
}
#if !CONFIG_SERIAL_CPU_INIT
if(cpu==bsp_cpu) {
if (IS_ENABLED(CONFIG_PARALLEL_CPU_INIT) && (cpu==bsp_cpu))
continue;
}
#endif
if (!cpu->enabled) {
continue;
@ -458,9 +456,9 @@ static void start_other_cpus(struct bus *cpu_bus, device_t bsp_cpu)
printk(BIOS_ERR, "CPU 0x%02x would not start!\n",
cpu->path.apic.apic_id);
}
#if CONFIG_SERIAL_CPU_INIT
udelay(10);
#endif
if (!IS_ENABLED(CONFIG_PARALLEL_CPU_INIT))
udelay(10);
}
}
@ -538,19 +536,17 @@ void initialize_cpus(struct bus *cpu_bus)
#endif
#if CONFIG_SMP && CONFIG_MAX_CPUS > 1
#if !CONFIG_SERIAL_CPU_INIT
/* start all aps at first, so we can init ECC all together */
start_other_cpus(cpu_bus, info->cpu);
#endif
if (IS_ENABLED(CONFIG_PARALLEL_CPU_INIT))
start_other_cpus(cpu_bus, info->cpu);
#endif
/* Initialize the bootstrap processor */
cpu_initialize(0);
#if CONFIG_SMP && CONFIG_MAX_CPUS > 1
#if CONFIG_SERIAL_CPU_INIT
start_other_cpus(cpu_bus, info->cpu);
#endif
if (!IS_ENABLED(CONFIG_PARALLEL_CPU_INIT))
start_other_cpus(cpu_bus, info->cpu);
/* Now wait the rest of the cpus stop*/
wait_other_cpus_stop(cpu_bus);

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@ -16,7 +16,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_PIRQ_TABLE
select SB_HT_CHAIN_UNITID_OFFSET_ONLY
select LIFT_BSP_APIC_ID
select SERIAL_CPU_INIT
select AMDMCT
select HAVE_MP_TABLE
select HAVE_ACPI_TABLES

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@ -18,7 +18,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_ACPI_TABLES
select SB_HT_CHAIN_UNITID_OFFSET_ONLY
select LIFT_BSP_APIC_ID
select SERIAL_CPU_INIT
select AMDMCT
select BOARD_ROMSIZE_KB_2048
select ENABLE_APIC_EXT_ID

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@ -27,7 +27,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select NORTHBRIDGE_AMD_CIMX_RD890
select SOUTHBRIDGE_AMD_CIMX_SB700
select SUPERIO_SMSC_SCH4037
select SERIAL_CPU_INIT
select BOARD_ROMSIZE_KB_2048
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE

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@ -28,7 +28,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select SERIAL_CPU_INIT
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_2048
select ENABLE_APIC_EXT_ID

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@ -14,7 +14,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_MP_TABLE
select SB_HT_CHAIN_UNITID_OFFSET_ONLY
select LIFT_BSP_APIC_ID
select SERIAL_CPU_INIT
select AMDMCT
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_1024

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@ -28,7 +28,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select HAVE_ACPI_RESUME
select SERIAL_CPU_INIT
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_4096
select GFXUMA

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@ -28,7 +28,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select HAVE_ACPI_RESUME
select SERIAL_CPU_INIT
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_4096
select GFXUMA

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@ -29,7 +29,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select HAVE_ACPI_RESUME
select SERIAL_CPU_INIT
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_4096
select GFXUMA

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@ -11,6 +11,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select SOUTHBRIDGE_AMD_AMD8111
select SOUTHBRIDGE_AMD_AMD8131
select SUPERIO_WINBOND_W83627HF
select PARALLEL_CPU_INIT
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
@ -66,10 +67,6 @@ config HT_CHAIN_UNITID_BASE
hex
default 0xa
config SERIAL_CPU_INIT
bool
default n
config IRQ_SLOT_COUNT
int
default 11

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@ -13,7 +13,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select SB_HT_CHAIN_UNITID_OFFSET_ONLY
select SERIAL_CPU_INIT
select AMDMCT
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_1024

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@ -28,7 +28,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select SERIAL_CPU_INIT
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_4096
select GFXUMA

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@ -28,7 +28,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select HAVE_ACPI_RESUME
select SERIAL_CPU_INIT
select HAVE_ACPI_TABLES
select SUPERIO_SMSC_LPC47N217
select BOARD_ROMSIZE_KB_4096

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@ -14,7 +14,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_MP_TABLE
select SB_HT_CHAIN_UNITID_OFFSET_ONLY
select LIFT_BSP_APIC_ID
select SERIAL_CPU_INIT
select AMDMCT
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_1024

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@ -30,7 +30,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select SERIAL_CPU_INIT
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_2048
select ENABLE_APIC_EXT_ID

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@ -27,7 +27,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select SERIAL_CPU_INIT
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_2048
select GFXUMA

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@ -29,7 +29,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select SERIAL_CPU_INIT
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_4096
select GFXUMA

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@ -29,7 +29,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select HAVE_ACPI_RESUME
select SERIAL_CPU_INIT
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_4096
select GFXUMA

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@ -29,7 +29,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select HAVE_ACPI_RESUME
select SERIAL_CPU_INIT
select HAVE_ACPI_TABLES
select SUPERIO_ITE_IT8712F
select BOARD_ROMSIZE_KB_8192

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@ -30,6 +30,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select MCP55_USE_AZA
select SUPERIO_ITE_IT8716F
select SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL
select PARALLEL_CPU_INIT
select HAVE_OPTION_TABLE
select HAVE_MP_TABLE
select LIFT_BSP_APIC_ID
@ -84,8 +85,4 @@ config HT_CHAIN_END_UNITID_BASE
hex
default 0x20
config SERIAL_CPU_INIT
bool
default n
endif # BOARD_ASUS_M2N_E

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@ -13,7 +13,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_MP_TABLE
select SB_HT_CHAIN_UNITID_OFFSET_ONLY
select LIFT_BSP_APIC_ID
select SERIAL_CPU_INIT
select AMDMCT
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_1024

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@ -14,7 +14,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_MP_TABLE
select SB_HT_CHAIN_UNITID_OFFSET_ONLY
select LIFT_BSP_APIC_ID
select SERIAL_CPU_INIT
select AMDMCT
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_1024

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@ -16,7 +16,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_MP_TABLE
select SB_HT_CHAIN_UNITID_OFFSET_ONLY
select LIFT_BSP_APIC_ID
select SERIAL_CPU_INIT
select AMDMCT
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_1024

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@ -14,7 +14,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_PIRQ_TABLE
select SB_HT_CHAIN_UNITID_OFFSET_ONLY
select LIFT_BSP_APIC_ID
select SERIAL_CPU_INIT
select AMDMCT
select HAVE_MP_TABLE
select HAVE_ACPI_TABLES

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@ -16,7 +16,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_PIRQ_TABLE
select SB_HT_CHAIN_UNITID_OFFSET_ONLY
select LIFT_BSP_APIC_ID
select SERIAL_CPU_INIT
select AMDMCT
select HAVE_MP_TABLE
select HAVE_ACPI_TABLES

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@ -7,6 +7,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select NORTHBRIDGE_AMD_AMDK8
select SOUTHBRIDGE_SIS_SIS966
select SUPERIO_ITE_IT8716F
select PARALLEL_CPU_INIT
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
@ -64,10 +65,6 @@ config HT_CHAIN_END_UNITID_BASE
hex
default 0x20
config SERIAL_CPU_INIT
bool
default n
config IRQ_SLOT_COUNT
int
default 11

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@ -10,6 +10,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select MCP55_USE_AZA
select SUPERIO_ITE_IT8716F
select SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL
select PARALLEL_CPU_INIT
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
@ -68,10 +69,6 @@ config HT_CHAIN_END_UNITID_BASE
hex
default 0x20
config SERIAL_CPU_INIT
bool
default n
config IRQ_SLOT_COUNT
int
default 11

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@ -14,7 +14,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_MP_TABLE
select SB_HT_CHAIN_UNITID_OFFSET_ONLY
select LIFT_BSP_APIC_ID
select SERIAL_CPU_INIT
select AMDMCT
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_1024

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@ -14,7 +14,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_MP_TABLE
select SB_HT_CHAIN_UNITID_OFFSET_ONLY
select LIFT_BSP_APIC_ID
select SERIAL_CPU_INIT
select AMDMCT
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_1024

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@ -14,7 +14,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_MP_TABLE
select SB_HT_CHAIN_UNITID_OFFSET_ONLY
select LIFT_BSP_APIC_ID
select SERIAL_CPU_INIT
select AMDMCT
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_1024

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@ -29,7 +29,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select HAVE_ACPI_RESUME
select SERIAL_CPU_INIT
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_2048
select GFXUMA

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@ -30,7 +30,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_MP_TABLE
select HAVE_ACPI_RESUME
select HAVE_SMI_HANDLER
select SERIAL_CPU_INIT
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_4096
select GFXUMA

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@ -7,6 +7,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select SOUTHBRIDGE_AMD_AMD8111
select SOUTHBRIDGE_AMD_AMD8131
select SUPERIO_NSC_PC87366
select PARALLEL_CPU_INIT
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
@ -54,10 +55,6 @@ config HT_CHAIN_UNITID_BASE
hex
default 0x1
config SERIAL_CPU_INIT
bool
default n
config IRQ_SLOT_COUNT
int
default 12

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@ -7,6 +7,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select SOUTHBRIDGE_AMD_AMD8111
select SOUTHBRIDGE_AMD_AMD8131
select SUPERIO_NSC_PC87366
select PARALLEL_CPU_INIT
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
@ -54,10 +55,6 @@ config HT_CHAIN_UNITID_BASE
hex
default 0x1
config SERIAL_CPU_INIT
bool
default n
config IRQ_SLOT_COUNT
int
default 12

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@ -14,7 +14,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_MP_TABLE
select SB_HT_CHAIN_UNITID_OFFSET_ONLY
select LIFT_BSP_APIC_ID
select SERIAL_CPU_INIT
select AMDMCT
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_1024

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@ -7,6 +7,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select SOUTHBRIDGE_AMD_AMD8111
select SOUTHBRIDGE_AMD_AMD8131
select SUPERIO_WINBOND_W83627HF
select PARALLEL_CPU_INIT
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
@ -49,10 +50,6 @@ config HT_CHAIN_UNITID_BASE
hex
default 0xa
config SERIAL_CPU_INIT
bool
default n
config IRQ_SLOT_COUNT
int
default 11

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@ -7,6 +7,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select SOUTHBRIDGE_AMD_AMD8111
select SOUTHBRIDGE_AMD_AMD8131
select SUPERIO_WINBOND_W83627HF
select PARALLEL_CPU_INIT
select HAVE_PIRQ_TABLE
select HAVE_OPTION_TABLE
select HAVE_MP_TABLE
@ -48,10 +49,6 @@ config HT_CHAIN_UNITID_BASE
hex
default 0x1
config SERIAL_CPU_INIT
bool
default n
config IRQ_SLOT_COUNT
int
default 12

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@ -7,6 +7,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select SOUTHBRIDGE_AMD_AMD8111
select SOUTHBRIDGE_AMD_AMD8131
select SUPERIO_WINBOND_W83627THG
select PARALLEL_CPU_INIT
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
@ -47,10 +48,6 @@ config HT_CHAIN_UNITID_BASE
hex
default 0x1
config SERIAL_CPU_INIT
bool
default n
config IRQ_SLOT_COUNT
int
default 9

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@ -30,7 +30,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select HAVE_ACPI_RESUME
select SERIAL_CPU_INIT
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_2048
select GFXUMA

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@ -14,7 +14,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_MP_TABLE
select SB_HT_CHAIN_UNITID_OFFSET_ONLY
select LIFT_BSP_APIC_ID
select SERIAL_CPU_INIT
select AMDMCT
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_1024

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@ -33,7 +33,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
# erases 28 KB and writes 10 KB register dumps to SPI flash on every
# boot, wasting 3 s and causing wear! Therefore disable S3 for now.
#select HAVE_ACPI_RESUME
select SERIAL_CPU_INIT
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_4096
select GFXUMA

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@ -35,7 +35,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
# erases 28 KB and writes 10 KB register dumps to SPI flash on every
# boot, wasting 3 s and causing wear! Therefore disable S3 for now.
#select HAVE_ACPI_RESUME
select SERIAL_CPU_INIT
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_4096
select GFXUMA

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@ -9,6 +9,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select MCP55_USE_NIC
select MCP55_USE_AZA
select SUPERIO_WINBOND_W83627EHG
select PARALLEL_CPU_INIT
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
@ -66,10 +67,6 @@ config HT_CHAIN_END_UNITID_BASE
hex
default 0x20
config SERIAL_CPU_INIT
bool
default n
config IRQ_SLOT_COUNT
int
default 11

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@ -8,6 +8,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select NORTHBRIDGE_AMD_AMDK8
select SOUTHBRIDGE_NVIDIA_MCP55
select SUPERIO_WINBOND_W83627EHG
select PARALLEL_CPU_INIT
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
@ -60,10 +61,6 @@ config HT_CHAIN_END_UNITID_BASE
hex
default 0x20
config SERIAL_CPU_INIT
bool
default n
config IRQ_SLOT_COUNT
int
default 11

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@ -93,10 +93,6 @@ config VAR_MTRR_HOLE
bool
default n
config SERIAL_CPU_INIT
bool
default y
config APIC_ID_OFFSET
hex
default 0x00

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@ -10,6 +10,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select MCP55_USE_NIC
select MCP55_USE_AZA
select SUPERIO_WINBOND_W83627EHG
select PARALLEL_CPU_INIT
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
@ -70,10 +71,6 @@ config HT_CHAIN_END_UNITID_BASE
hex
default 0x20
config SERIAL_CPU_INIT
bool
default n
config IRQ_SLOT_COUNT
int
default 11

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@ -10,6 +10,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select MCP55_USE_NIC
select MCP55_USE_AZA
select SUPERIO_WINBOND_W83627HF
select PARALLEL_CPU_INIT
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
@ -83,8 +84,4 @@ config AMD_UCODE_PATCH_FILE
string
default "mc_patch_0100009f.h"
config SERIAL_CPU_INIT
bool
default n
endif # BOARD_SUPERMICRO_H8DMR_FAM10

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@ -32,7 +32,6 @@ config BOARD_SPECIFIC_OPTIONS
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select SERIAL_CPU_INIT
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_2048
#select MMCONF_SUPPORT_DEFAULT #TODO enable it to resolve Multicore IO conflict

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@ -82,8 +82,4 @@ config AMD_UCODE_PATCH_FILE
string
default "mc_patch_0100009f.h"
config SERIAL_CPU_INIT
bool
default y
endif # BOARD_SUPERMICRO_H8QME_FAM10

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@ -32,7 +32,6 @@ config BOARD_SPECIFIC_OPTIONS
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select SERIAL_CPU_INIT
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_4096

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@ -17,7 +17,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_ACPI_TABLES
select SB_HT_CHAIN_UNITID_OFFSET_ONLY
select LIFT_BSP_APIC_ID
select SERIAL_CPU_INIT
select AMDMCT
select BOARD_ROMSIZE_KB_2048
select ENABLE_APIC_EXT_ID

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@ -10,7 +10,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select SERIAL_CPU_INIT
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_512
select SB_HT_CHAIN_UNITID_OFFSET_ONLY

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@ -10,7 +10,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select SERIAL_CPU_INIT
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_1024
select QRANK_DIMM_SUPPORT

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@ -10,7 +10,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select SERIAL_CPU_INIT
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_1024
select QRANK_DIMM_SUPPORT

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@ -9,6 +9,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select SOUTHBRIDGE_NVIDIA_MCP55
select MCP55_USE_NIC
select SUPERIO_WINBOND_W83627HF
select PARALLEL_CPU_INIT
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
@ -65,10 +66,6 @@ config HT_CHAIN_END_UNITID_BASE
hex
default 0x20
config SERIAL_CPU_INIT
bool
default n
config IRQ_SLOT_COUNT
int
default 11

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@ -9,6 +9,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select SOUTHBRIDGE_NVIDIA_MCP55
select MCP55_USE_NIC
select SUPERIO_WINBOND_W83627HF
select PARALLEL_CPU_INIT
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
@ -63,10 +64,6 @@ config HT_CHAIN_END_UNITID_BASE
hex
default 0x20
config SERIAL_CPU_INIT
bool
default n
config IRQ_SLOT_COUNT
int
default 11

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@ -32,7 +32,6 @@ config BOARD_SPECIFIC_OPTIONS
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select SERIAL_CPU_INIT
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_4096
#select MMCONF_SUPPORT_DEFAULT #TODO enable it to resolve Multicore IO conflict

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@ -9,7 +9,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select SERIAL_CPU_INIT
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_512
select SB_HT_CHAIN_UNITID_OFFSET_ONLY