mb/facebook/fbg1701: Add Kingston B511ECMDXGGB memory support
FBG-1701 revision 1.3 will use Kingston onboard memory. Add Kingston SPD file. When Samsung memory configuration is disabled use cpld_read_pcb_version() for using correct SPD data. BUG=N/A TEST=Boot and verified on Facebook FBG-1701 revision 1.3 Change-Id: I2e1d1b933d5a49a7005685ed530c882429019027 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35792 Reviewed-by: Wim Vervoorn Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Frans Hendriks
Felix Held
parent
9f96568171
commit
5c540f5c52
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@ -42,3 +42,4 @@ logo.bmp-compression := LZMA
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# Order of names in SPD_SOURCES is important!
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SPD_SOURCES = SAMSUNG_K4B8G1646D-MYKO
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SPD_SOURCES += MICRON_MT41K512M16HA-125A
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SPD_SOURCES += KINGSTON_B5116ECMDXGGB
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@ -29,14 +29,21 @@
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#include <spd_bin.h>
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#include <stdint.h>
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#include "cpld.h"
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void mainboard_memory_init_params(struct romstage_params *params,
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MEMORY_INIT_UPD *memory_params)
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{
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struct region_device spd_rdev;
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u8 spd_index = 0;
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if (!CONFIG(ONBOARD_SAMSUNG_MEM))
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spd_index = 1;
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if (!CONFIG(ONBOARD_SAMSUNG_MEM)) {
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if (cpld_read_pcb_version() <= 7)
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spd_index = 1;
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else
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spd_index = 2;
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}
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if (get_spd_cbfs_rdev(&spd_rdev, spd_index) < 0)
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die("spd.bin not found\n");
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@ -0,0 +1,258 @@
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#
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# This file is part of the coreboot project.
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#
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# Copyright (C) 2019 Facebook, Inc.
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# Copyright (C) 2019 Eltan B.V.
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; version 2 of the License.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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#
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# 8 Gb DDR3 (1600 MHz 11-11-11) Kingston B5116ECMDXGGB
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#
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# SINGLE DIE
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#
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# 64Mx16x8 ( 8 bank, 16 Rows, 10 Col, 2 KB page size )
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# 6-7-8-9-10-11
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# DDR3L-1600
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# tCk 1.25ns
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# tRCD 13.75ns
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# tRP 13.75ns
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# tRAS 35ns
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# tRC 48.75ns
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# CL-tRCD-tRP 11-11-11
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# 0 Number of SPD Bytes used / Total SPD Size / CRC Coverage
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# bits[3:0]: 3 = 384 SPD Bytes Used
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# bits[6:4]: 1 = 256 SPD Bytes Total
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# bit7 : 0 = CRC covers bytes 0 ~ 128
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23
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# 1 SPD Revision
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# 0x10 = Revision 1.0
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10
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# 2 Key Byte / DRAM Device Type
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# bits[7:0]: 0x0c = DDR3 SDRAM
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0B
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# 3 Key Byte / Module Type
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# bits[3:0]: 3 = SODIMM
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# bits[6:4]: 0 = Not hybrid
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# bits[7]: 0 = Not hybrid
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03
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# 4 SDRAM CHIP Density and Banks
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# bits[3:0]: 5 = 8 Gigabits Total SDRAM capacity per chip
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# bits[6:4]: 0 = 3 (8 banks)
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# bits[7]: reserverd
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05
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# 5 SDRAM Addressing
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# bits[2:0]: 1 = 10 Column Address Bits
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# bits[5:3]: 4 = 16 Row Address Bits
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# bits[7:6]: 0 = reserved
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21
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# 6 Module Nominal Voltage
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# bits[0]: 0 = 1.5V operable
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# bits[1]: 1 = 1.35V operable
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# bits[2]: 0 = NOT 1.25V operable
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# bits[7:3]: reserved
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02
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# 7 Module Organization
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# bits[2:0]: 010b = 16 bits SDRAM device
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# bits[5:3]: 000b = 1 ranks
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# bits[7:6]: reserved
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02
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# 8 Module Memory Bus width
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# bits[2:0]: 3 = 64 bits pirmary bus width
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# bits[4:3]: 0 = 0 bits bus witdth extension
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# bits[7:5]: reserved
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03
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# 9 Fine Timebase (FTB) dividend / divisor
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# bits[3:0]: 1 = Divisor
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# bits[7:4]: 1 = Dividend
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11
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# 10 Medium Timebase (MTB) dividend
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# bits[7:0]: 0 = 1 (timebase 0.125ns)
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01
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# 11 Medium Timebase (MTB) divisor
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# bits[7:0]: 8 (timebase 0.125ns)
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08
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# 12 SDRAM Minimum cycle time (tCKmin)
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# 0xA tCK = 1.25ns (DDR3-1600 (800 MHz clock))
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0A
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# 13 Reserved
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00
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# 14 CAS Latencies supported, Least Significate Byte
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# Support 6,7,8,9,10,11
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FC
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# 15 CAS Latencies supported, Most Significate Byte
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# No supporting CL 12-18
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00
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# 16 Minimum CAS Latency Time (tAAmin)
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# 0x69 tAA = 13.125ns (offset = 00) DDR3-1600K downbin
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69
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# 17 Minimum Write Recovery Time (tWRmin)
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# 0x78 tWR = 15 ns
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78
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# 18 Minimum RAS to CAS Delay Time (tRCDmin)
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# 0x69 tRCD = 13.125ns (offset 00) DDR3-1600K downbin
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69
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# 19 Minimum Row Active to Row Active Delay Time (tRRDmin)
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# 0x3C tRRD = 7.5ns DDR3-1600, 2KB
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3C
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# 20 Minimum Row Precharge Delay Time (tRPmin)
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# 0x69 tRP = 13.125ns (offset 00) DDR3-1600K downbin
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69
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# 21 Upper Nibble for tRAS and tRC
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# 3:0 : 1 higher tRAS = 35ns
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# 7:0 : 1 higher tRC = 48.125ns
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11
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# 22 Minimum Active to Precharge Delay Time (tRASmin), Least Significant byte
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# lower 0x118 : tRAS = 35ns DDR3-1600
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18
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# 23 Minimum Active to Precharge Delay Time (tRCmin), Most Significant byte
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# lower 0x181 : tRC = 48.125ns (offset 00) DDR3-1600K downbin
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81
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# 24 Minimum Refresh Recovery Delay time (tRFCmin), Least Significant byte
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# lower 0xAF0 : tRFC = 350ns 8 Gb
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F0
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# 25 Minimum Refresh Recovery Delay time (tRFCmin), Most Significant byte
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# higher 0xAF0 : tRFC = 350ns 8 Gb
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0A
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# 26 tWTRmin
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# 0x3C : tWTR = 7.5 ns (DDR3)
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3C
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# 27 tRTPmin
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# 0x3C : tRTP = 7.5 ns (DDR3)
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3C
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# 28 Upper Nibble for tFAW
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# Bit [3:0] : 1 = higher 0x140 tFAW = 40ns
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01
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# 29 tFAWmin Lower
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# lower 0x140 : tFAW = 40ns
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40
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# 30 SDRAM Optional Features
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# byte [0] : 1 = RZQ/6 is support
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# byte [1] : 1 = RZQ/7 is supported
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# byte [7] : 1 = DLL-Off Mode support
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83
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# 31 Thermal options
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# byte [0] : 1 = 0 - 95C
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# byte [2] : 0 = Auto Self Refresh (ASR) is not supported
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# byte [7] : 0 = Partial Array Self Refres (PASR) is not supported
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01
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# 32 Module Thermal support
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# byte [0] : 0 = Thermal sensor accuracy undefined
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# byte [7] : 0 = No thermal sensor
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00
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# 33 SDRAM device type
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# byte [1:0] : 00b = Signal Loading not specified
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# byte [6:4] : 000b = Die count not specified
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# byte [7] : 0 = Standard Monolithic DRAM Device
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00
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# 34 Fine tCKmin
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# 0x00 tCK = 1.25ns (DDR3-1600 (800 MHz clock))
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00
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# 35 Fine tAAmin
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# 0x00 tAA = 13.125ns (tAAmin offset = 00) DDR3-1600K downbin
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00
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# 36 Fine tRCDmin
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# 0x00 tRCD = 13.125ns DDR3-1600K downbin
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00
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# 37 Fine tRPmin
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# 0x00 tRP = 13.125ns (offset 00) DDR3-1600K downbin
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00
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# 38 Fine tRCmin
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# 0x00 tRC = 48.125ns (offset 00) DDR3-1600K downbin
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00
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# 39-59 reserved, general section
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00
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# 60-116 Module specific section
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00
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# 117-118 Module Manufacturer
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01 98
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# 119 Module Manufacturing Location
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00
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# 120-121 Module Manufacturing Date
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13 0A
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# 122-125 Module Serial number
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00 00 00 00
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# 126-127 SPD CRC
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00 00
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# 128-145 Module Part number
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66 53 49 49 54 69 67 77 68 88 71 71 66 00 00 00
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00 00
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# 145-146 Module revision code
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00 00
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# 148-149 DRAM Manufacturer ID code
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01 98
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# 150-175 Manufacturer Specific Data
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00
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# 176-255 Open for Customer Use
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# 176 - 255
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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