AMD K8 (rev F): Move MEM_TRAIN_SEQ check to northbridge

Do it just to remove MEM_TRAIN_SEQ test under mainboard/ to see all
K8 rev F boards do the same things here.

Change-Id: If75035a4ef8882c2618d434d83ba59c408593d86
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4567
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

src/mainboard/amd/serengeti_cheetah/romstage.c

@@ -135,9 +135,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
 
-#if CONFIG_MEM_TRAIN_SEQ == 1
         set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
-#endif
 	setup_coherent_ht_domain(); // routing table and start other core0
 
 	wait_all_core0_started();

src/mainboard/asus/m2n-e/romstage.c

@@ -121,10 +121,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo, sysinfo + 1);
 	printk(BIOS_DEBUG, "bsp_apicid=0x%02x\n", bsp_apicid);
 
-#if CONFIG_MEM_TRAIN_SEQ == 1
 	/* In BSP so could hold all AP until sysinfo is in RAM. */
 	set_sysinfo_in_ram(0);
-#endif
 
 	setup_coherent_ht_domain(); /* Routing table and start other core0. */
 	wait_all_core0_started();

src/mainboard/gigabyte/ga_2761gxdk/romstage.c

@@ -145,9 +145,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
         print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
 
-#if CONFIG_MEM_TRAIN_SEQ == 1
         set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
-#endif
         setup_coherent_ht_domain(); // routing table and start other core0
 
         wait_all_core0_started();

src/mainboard/gigabyte/m57sli/romstage.c

@@ -148,9 +148,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
         print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
 
-#if CONFIG_MEM_TRAIN_SEQ == 1
         set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
-#endif
         setup_coherent_ht_domain(); // routing table and start other core0
 
         wait_all_core0_started();

src/mainboard/hp/dl145_g3/romstage.c

@@ -158,9 +158,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
 	printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid);
 
-#if CONFIG_MEM_TRAIN_SEQ == 1
 	set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
-#endif
 	setup_coherent_ht_domain();
 
 	wait_all_core0_started();

src/mainboard/msi/ms7260/romstage.c

@@ -139,10 +139,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	print_debug_hex8(bsp_apicid);
 	print_debug("\n");
 
-#if CONFIG_MEM_TRAIN_SEQ == 1
 	/* In BSP so could hold all AP until sysinfo is in RAM. */
 	set_sysinfo_in_ram(0);
-#endif
 
 	setup_coherent_ht_domain(); /* Routing table and start other core0. */
 	wait_all_core0_started();

src/mainboard/nvidia/l1_2pvv/romstage.c

@@ -137,9 +137,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
 
-#if CONFIG_MEM_TRAIN_SEQ == 1
 	set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
-#endif
 	setup_coherent_ht_domain(); // routing table and start other core0
 
 	wait_all_core0_started();

src/mainboard/supermicro/h8dme/romstage.c

@@ -205,9 +205,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	print_debug_hex8(bsp_apicid);
 	print_debug("\n");
 
-#if CONFIG_MEM_TRAIN_SEQ == 1
 	set_sysinfo_in_ram(0);	// in BSP so could hold all ap until sysinfo is in ram
-#endif
 /*	dump_smbus_registers(); */
 	setup_coherent_ht_domain();	// routing table and start other core0
 

src/mainboard/supermicro/h8dmr/romstage.c

@@ -132,9 +132,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
         print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
 
-#if CONFIG_MEM_TRAIN_SEQ == 1
         set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
-#endif
         setup_coherent_ht_domain(); // routing table and start other core0
 
         wait_all_core0_started();

src/mainboard/tyan/s2912/romstage.c

@@ -135,9 +135,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
 
-#if CONFIG_MEM_TRAIN_SEQ == 1
 	set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
-#endif
 	setup_coherent_ht_domain(); // routing table and start other core0
 
 	wait_all_core0_started();

src/northbridge/amd/amdk8/raminit_f_dqs.c

@@ -1793,6 +1793,7 @@ static void clear_mtrr_dqs(unsigned tom2_k)
 	}
 }
 
+#if CONFIG_MEM_TRAIN_SEQ == 1
 static void set_htic_bit(unsigned i, unsigned val, unsigned bit)
 {
 	uint32_t dword;
@@ -1802,8 +1803,6 @@ static void set_htic_bit(unsigned i, unsigned val, unsigned bit)
 	pci_write_config32(PCI_DEV(0, 0x18+i, 0), HT_INIT_CONTROL, dword);
 }
 
-
-#if CONFIG_MEM_TRAIN_SEQ == 1
 static unsigned get_htic_bit(unsigned i, unsigned bit)
 {
 	uint32_t dword;
@@ -1822,7 +1821,9 @@ static void wait_till_sysinfo_in_ram(void)
 
 static void set_sysinfo_in_ram(unsigned val)
 {
+#if CONFIG_MEM_TRAIN_SEQ == 1
 	set_htic_bit(0, val, 9);
+#endif
 }
 
 #if CONFIG_HAVE_ACPI_RESUME