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mb/google/volteer: clang-format mainboard.c

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BUG=None
TEST=abuild -t GOOGLE_VOLTEER2 -c max -x

Change-Id: Ibdd8cc2222e7af11c11df963b088ca2db07a3214
Signed-off-by: Jes Bodi Klinke <jbk@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47048
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Jes Klinke 2020-10-30 13:23:14 -07:00 committed by Patrick Georgi
parent b5f580e03c
commit 5c7311a524
1 changed files with 7 additions and 10 deletions
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17
src/mainboard/google/volteer/mainboard.c
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@ -102,8 +102,7 @@ void mainboard_update_soc_chip_config(struct soc_intel_tigerlake_config *cfg)
return; return;
} }
if (CONFIG(MAINBOARD_HAS_SPI_TPM_CR50) && if (CONFIG(MAINBOARD_HAS_SPI_TPM_CR50) && cr50_is_long_interrupt_pulse_enabled()) {
cr50_is_long_interrupt_pulse_enabled()) {
printk(BIOS_INFO, "Enabling S0i3.4\n"); printk(BIOS_INFO, "Enabling S0i3.4\n");
} else { } else {
/* /*
@ -126,8 +125,7 @@ static void mainboard_chip_init(void *chip_info)
base_pads = variant_base_gpio_table(&base_num); base_pads = variant_base_gpio_table(&base_num);
override_pads = variant_override_gpio_table(&override_num); override_pads = variant_override_gpio_table(&override_num);
gpio_configure_pads_with_override(base_pads, base_num, gpio_configure_pads_with_override(base_pads, base_num, override_pads, override_num);
override_pads, override_num);
} }
void mainboard_silicon_init_params(FSP_S_CONFIG *params) void mainboard_silicon_init_params(FSP_S_CONFIG *params)
@ -135,14 +133,13 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *params)
bool has_usb4; bool has_usb4;
/* If device doesn't have USB4 hardware, disable tbt */ /* If device doesn't have USB4 hardware, disable tbt */
has_usb4 = (fw_config_probe(FW_CONFIG(DB_USB, USB4_GEN2)) || has_usb4 = (fw_config_probe(FW_CONFIG(DB_USB, USB4_GEN2))
fw_config_probe(FW_CONFIG(DB_USB, USB4_GEN3))); || fw_config_probe(FW_CONFIG(DB_USB, USB4_GEN3)));
if (!has_usb4) if (!has_usb4)
memset(params->ITbtPcieRootPortEn, memset(params->ITbtPcieRootPortEn, 0,
0, ARRAY_SIZE(params->ITbtPcieRootPortEn)
ARRAY_SIZE(params->ITbtPcieRootPortEn) * * sizeof(*params->ITbtPcieRootPortEn));
sizeof(*params->ITbtPcieRootPortEn));
} }
struct chip_operations mainboard_ops = { struct chip_operations mainboard_ops = {