mb/google/volteer: clang-format mainboard.c
This CL is entirely generated by running the automatic formatter on this one file. BUG=None TEST=abuild -t GOOGLE_VOLTEER2 -c max -x Change-Id: Ibdd8cc2222e7af11c11df963b088ca2db07a3214 Signed-off-by: Jes Bodi Klinke <jbk@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47048 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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@ -102,8 +102,7 @@ void mainboard_update_soc_chip_config(struct soc_intel_tigerlake_config *cfg)
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return;
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}
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if (CONFIG(MAINBOARD_HAS_SPI_TPM_CR50) &&
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cr50_is_long_interrupt_pulse_enabled()) {
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if (CONFIG(MAINBOARD_HAS_SPI_TPM_CR50) && cr50_is_long_interrupt_pulse_enabled()) {
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printk(BIOS_INFO, "Enabling S0i3.4\n");
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} else {
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/*
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@ -126,8 +125,7 @@ static void mainboard_chip_init(void *chip_info)
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base_pads = variant_base_gpio_table(&base_num);
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override_pads = variant_override_gpio_table(&override_num);
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gpio_configure_pads_with_override(base_pads, base_num,
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override_pads, override_num);
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gpio_configure_pads_with_override(base_pads, base_num, override_pads, override_num);
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}
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void mainboard_silicon_init_params(FSP_S_CONFIG *params)
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@ -135,14 +133,13 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *params)
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bool has_usb4;
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/* If device doesn't have USB4 hardware, disable tbt */
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has_usb4 = (fw_config_probe(FW_CONFIG(DB_USB, USB4_GEN2)) ||
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fw_config_probe(FW_CONFIG(DB_USB, USB4_GEN3)));
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has_usb4 = (fw_config_probe(FW_CONFIG(DB_USB, USB4_GEN2))
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|| fw_config_probe(FW_CONFIG(DB_USB, USB4_GEN3)));
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if (!has_usb4)
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memset(params->ITbtPcieRootPortEn,
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0,
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ARRAY_SIZE(params->ITbtPcieRootPortEn) *
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sizeof(*params->ITbtPcieRootPortEn));
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memset(params->ITbtPcieRootPortEn, 0,
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ARRAY_SIZE(params->ITbtPcieRootPortEn)
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* sizeof(*params->ITbtPcieRootPortEn));
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}
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struct chip_operations mainboard_ops = {
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