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nb/intel/nehalem/gma: Use common init_igd_opregion method 

Use common init_igd_opregion method.

Change-Id: Ic8a85d1373f04814b4460cce377d6e096bcdc349
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19907
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Patrick Rudolph 2017-05-17 19:39:12 +02:00 committed by Nico Huber
parent d65ff22988
commit 5c82026ca6
4 changed files with 38 additions and 156 deletions
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1
src/northbridge/intel/nehalem/Kconfig
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@ -21,6 +21,7 @@ config NORTHBRIDGE_INTEL_NEHALEM
select TSC_MONOTONIC_TIMER select TSC_MONOTONIC_TIMER
select INTEL_GMA_ACPI select INTEL_GMA_ACPI
select NORTHBRIDGE_INTEL_COMMON_MRC_CACHE select NORTHBRIDGE_INTEL_COMMON_MRC_CACHE
select NORTHBRIDGE_INTEL_COMMON_GMA_OPREGION
select ACPI_HUGE_LOWMEM_BACKUP select ACPI_HUGE_LOWMEM_BACKUP
select HAVE_LINEAR_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT select HAVE_LINEAR_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT
select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT

138
src/northbridge/intel/nehalem/acpi.c
View File

@ -19,18 +19,9 @@
#define __SIMPLE_DEVICE__ #define __SIMPLE_DEVICE__
#include <types.h> #include <types.h>
#include <string.h>
#include <console/console.h>
#include <arch/io.h>
#include <arch/acpi.h>
#include <device/device.h> #include <device/device.h>
#include <device/pci.h> #include <device/pci.h>
#include <device/pci_ids.h> #include <device/pci_ids.h>
#include <drivers/intel/gma/intel_bios.h>
#include <arch/acpigen.h>
#include <cpu/cpu.h>
#include <drivers/intel/gma/i915.h>
#include <cbmem.h>
#include "nehalem.h" #include "nehalem.h"
unsigned long acpi_fill_mcfg(unsigned long current) unsigned long acpi_fill_mcfg(unsigned long current)
@ -76,132 +67,3 @@ unsigned long acpi_fill_mcfg(unsigned long current)
return current; return current;
} }
static void *get_intel_vbios(void)
{
/* This should probably be looking at CBFS or we should always
* deploy the VBIOS on Intel systems, even if we don't run it
* in coreboot (e.g. SeaBIOS only scenarios).
*/
u8 *vbios = (u8 *) 0xc0000;
optionrom_header_t *oprom = (optionrom_header_t *) vbios;
optionrom_pcir_t *pcir = (optionrom_pcir_t *) (vbios +
oprom->pcir_offset);
printk(BIOS_DEBUG, "GET_VBIOS: %x %x %x %x %x\n",
oprom->signature, pcir->vendor, pcir->classcode[0],
pcir->classcode[1], pcir->classcode[2]);
if ((oprom->signature == OPROM_SIGNATURE) &&
(pcir->vendor == PCI_VENDOR_ID_INTEL) &&
(pcir->classcode[0] == 0x00) &&
(pcir->classcode[1] == 0x00) && (pcir->classcode[2] == 0x03))
return (void *)vbios;
return NULL;
}
static int init_opregion_vbt(igd_opregion_t * opregion)
{
void *vbios;
vbios = get_intel_vbios();
if (!vbios) {
printk(BIOS_DEBUG, "VBIOS not found.\n");
return 1;
}
printk(BIOS_DEBUG, " ... VBIOS found at %p\n", vbios);
optionrom_header_t *oprom = (optionrom_header_t *) vbios;
optionrom_vbt_t *vbt = (optionrom_vbt_t *) (vbios + oprom->vbt_offset);
if (read32(vbt->hdr_signature) != VBT_SIGNATURE) {
printk(BIOS_DEBUG, "VBT not found!\n");
return 1;
}
memcpy(opregion->header.vbios_version, vbt->coreblock_biosbuild, 4);
memcpy(opregion->vbt.gvd1, vbt, vbt->hdr_vbt_size < 7168 ?
vbt->hdr_vbt_size : 7168);
return 0;
}
/* Initialize IGD OpRegion, called from ACPI code */
int init_igd_opregion(igd_opregion_t * opregion)
{
pci_devfn_t igd;
u16 reg16;
memset((void *)opregion, 0, sizeof(igd_opregion_t));
// FIXME if IGD is disabled, we should exit here.
memcpy(&opregion->header.signature, IGD_OPREGION_SIGNATURE,
sizeof(opregion->header.signature));
/* 8kb */
opregion->header.size = sizeof(igd_opregion_t) / 1024;
opregion->header.version = IGD_OPREGION_VERSION;
// FIXME We just assume we're mobile for now
opregion->header.mailboxes = MAILBOXES_MOBILE;
// TODO Initialize Mailbox 1
// TODO Initialize Mailbox 3
opregion->mailbox3.bclp = IGD_BACKLIGHT_BRIGHTNESS;
opregion->mailbox3.pfit = IGD_FIELD_VALID | IGD_PFIT_STRETCH;
opregion->mailbox3.pcft = 0; // should be (IMON << 1) & 0x3e
opregion->mailbox3.cblv = IGD_FIELD_VALID | IGD_INITIAL_BRIGHTNESS;
opregion->mailbox3.bclm[0] = IGD_WORD_FIELD_VALID + 0x0000;
opregion->mailbox3.bclm[1] = IGD_WORD_FIELD_VALID + 0x0a19;
opregion->mailbox3.bclm[2] = IGD_WORD_FIELD_VALID + 0x1433;
opregion->mailbox3.bclm[3] = IGD_WORD_FIELD_VALID + 0x1e4c;
opregion->mailbox3.bclm[4] = IGD_WORD_FIELD_VALID + 0x2866;
opregion->mailbox3.bclm[5] = IGD_WORD_FIELD_VALID + 0x327f;
opregion->mailbox3.bclm[6] = IGD_WORD_FIELD_VALID + 0x3c99;
opregion->mailbox3.bclm[7] = IGD_WORD_FIELD_VALID + 0x46b2;
opregion->mailbox3.bclm[8] = IGD_WORD_FIELD_VALID + 0x50cc;
opregion->mailbox3.bclm[9] = IGD_WORD_FIELD_VALID + 0x5ae5;
opregion->mailbox3.bclm[10] = IGD_WORD_FIELD_VALID + 0x64ff;
init_opregion_vbt(opregion);
/* TODO This needs to happen in S3 resume, too.
* Maybe it should move to the finalize handler
*/
igd = PCI_DEV(0, 0x2, 0);
pci_write_config32(igd, ASLS, (u32) opregion);
reg16 = pci_read_config16(igd, SWSCI);
reg16 &= ~(1 << 0);
reg16 |= (1 << 15);
pci_write_config16(igd, SWSCI, reg16);
/* clear dmisci status */
reg16 = inw(DEFAULT_PMBASE + TCO1_STS);
reg16 |= DMISCI_STS; // reference code does an &=
outw(DEFAULT_PMBASE + TCO1_STS, reg16);
/* clear acpi tco status */
outl(DEFAULT_PMBASE + GPE0_STS, TCOSCI_STS);
/* enable acpi tco scis */
reg16 = inw(DEFAULT_PMBASE + GPE0_EN);
reg16 |= TCOSCI_EN;
outw(DEFAULT_PMBASE + GPE0_EN, reg16);
return 0;
}
void *igd_make_opregion(void)
{
igd_opregion_t *opregion;
printk(BIOS_DEBUG, "ACPI: * IGD OpRegion\n");
opregion = cbmem_add(CBMEM_ID_IGD_OPREGION, sizeof(*opregion));
if (opregion)
init_igd_opregion(opregion);
return opregion;
}

50
src/northbridge/intel/nehalem/gma.c
View File

@ -26,10 +26,11 @@
#include <cpu/x86/mtrr.h> #include <cpu/x86/mtrr.h>
#include <drivers/intel/gma/edid.h> #include <drivers/intel/gma/edid.h>
#include <drivers/intel/gma/i915.h> #include <drivers/intel/gma/i915.h>
#include <drivers/intel/gma/intel_bios.h>
#include <pc80/vga.h> #include <pc80/vga.h>
#include <pc80/vga_io.h> #include <pc80/vga_io.h>
#include <drivers/intel/gma/intel_bios.h>
#include <southbridge/intel/ibexpeak/nvs.h> #include <southbridge/intel/ibexpeak/nvs.h>
#include <northbridge/intel/common/gma_opregion.h>
#include <cbmem.h> #include <cbmem.h>
#include "chip.h" #include "chip.h"
@ -1099,27 +1100,50 @@ static void gma_ssdt(device_t device)
drivers_intel_gma_displays_ssdt_generate(gfx); drivers_intel_gma_displays_ssdt_generate(gfx);
} }
/* Enable SCI to ACPI _GPE._L06 */
static void gma_enable_swsci(void)
{
u16 reg16;
/* clear DMISCI status */
reg16 = inw(DEFAULT_PMBASE + TCO1_STS);
reg16 &= DMISCI_STS;
outw(DEFAULT_PMBASE + TCO1_STS, reg16);
/* clear acpi tco status */
outl(DEFAULT_PMBASE + GPE0_STS, TCOSCI_STS);
/* enable acpi tco scis */
reg16 = inw(DEFAULT_PMBASE + GPE0_EN);
reg16 |= TCOSCI_EN;
outw(DEFAULT_PMBASE + GPE0_EN, reg16);
}
static unsigned long static unsigned long
gma_write_acpi_tables(struct device *const dev, gma_write_acpi_tables(struct device *const dev,
unsigned long current, unsigned long current,
struct acpi_rsdp *const rsdp) struct acpi_rsdp *const rsdp)
{ {
igd_opregion_t *opregion; igd_opregion_t *opregion = (igd_opregion_t *)current;
global_nvs_t *gnvs; global_nvs_t *gnvs;
// FIXME: Replace by common VBT implementation writing to current if (init_igd_opregion(opregion) != CB_SUCCESS)
opregion = igd_make_opregion(); return current;
if (opregion) {
/* GNVS has been already set up */ current += sizeof(igd_opregion_t);
gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
if (gnvs) { /* GNVS has been already set up */
/* IGD OpRegion Base Address */ gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
gnvs->aslb = (u32)(uintptr_t)opregion; if (gnvs) {
} else { /* IGD OpRegion Base Address */
printk(BIOS_ERR, "Error: GNVS table not found.\n"); gnvs->aslb = (u32)(uintptr_t)opregion;
} } else {
printk(BIOS_ERR, "Error: GNVS table not found.\n");
} }
gma_enable_swsci();
current = acpi_align_current(current);
return current; return current;
} }

5
src/northbridge/intel/nehalem/nehalem.h
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@ -300,11 +300,6 @@ void dump_mem(unsigned start, unsigned end);
void report_platform_info(void); void report_platform_info(void);
#endif /* !__SMM__ */ #endif /* !__SMM__ */
#if !defined(__PRE_RAM__)
#include <drivers/intel/gma/opregion.h>
int init_igd_opregion(igd_opregion_t *igd_opregion);
#endif
#endif #endif
#endif #endif
#endif /* __NORTHBRIDGE_INTEL_NEHALEM_NEHALEM_H__ */ #endif /* __NORTHBRIDGE_INTEL_NEHALEM_NEHALEM_H__ */