dmp/vortex86ex: Merge northbridge and southbridge into soc

Change-Id: I16c04452d2d6c3205aea29fe8aa8fad8fc485a46
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14600
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

src/mainboard/dmp/vortex86ex/Kconfig

@@ -18,8 +18,7 @@ if BOARD_DMP_EX
 config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
 	select CPU_DMP_VORTEX86EX
-	select NORTHBRIDGE_DMP_VORTEX86EX
-	select SOUTHBRIDGE_DMP_VORTEX86EX
+	select SOC_DMP_VORTEX86EX
 	select HAVE_PIRQ_TABLE
 	select BOARD_ROMSIZE_KB_256
 	select ROMCC

src/mainboard/dmp/vortex86ex/devicetree.cb

@@ -13,18 +13,16 @@
 ## GNU General Public License for more details.
 ##
 
-chip northbridge/dmp/vortex86ex			# North Bridge
+chip soc/dmp/vortex86ex			# North Bridge
 	device domain 0 on
 		device pci 0.0 on end		# Host Bridge
-		chip southbridge/dmp/vortex86ex	# South Bridge
-			device pci 7.0 on end	# ISA Bridge
-			device pci 8.0 on end	# Ethernet
-			device pci a.0 on end	# USB 1.1
-			device pci a.1 on end	# USB 2.0
-			device pci b.0 on end	# USB 1.1
-			device pci b.1 on end	# USB 2.0
-			device pci c.0 on end	# IDE
-		end
+		device pci 7.0 on end	# ISA Bridge
+		device pci 8.0 on end	# Ethernet
+		device pci a.0 on end	# USB 1.1
+		device pci a.1 on end	# USB 2.0
+		device pci b.0 on end	# USB 1.1
+		device pci b.1 on end	# USB 2.0
+		device pci c.0 on end	# IDE
 	end # pci domain 0
 	chip cpu/dmp/vortex86ex end	# CPU
 end

src/mainboard/dmp/vortex86ex/romstage.c

@@ -22,9 +22,9 @@
 #include <cpu/x86/cache.h>
 #include <halt.h>
 #include "drivers/pc80/pc/i8254.c"
-#include <northbridge/dmp/vortex86ex/northbridge.h>
-#include <southbridge/dmp/vortex86ex/southbridge.h>
-#include "northbridge/dmp/vortex86ex/raminit.c"
+#include <soc/dmp/vortex86ex/northbridge.h>
+#include <soc/dmp/vortex86ex/southbridge.h>
+#include "soc/dmp/vortex86ex/raminit.c"
 #include <cpu/dmp/dmp_post_code.h>
 
 #define DMP_CPUID_SX      0x31504d44

src/northbridge/dmp/vortex86ex/Kconfig

@@ -1,18 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2013 DMP Electronics Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-
-config NORTHBRIDGE_DMP_VORTEX86EX
-	bool
-	select LATE_CBMEM_INIT

src/northbridge/dmp/vortex86ex/Makefile.inc

@@ -1,21 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2013 DMP Electronics Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-
-ifeq ($(CONFIG_NORTHBRIDGE_DMP_VORTEX86EX),y)
-
-ramstage-y += northbridge.c
-ramstage-y += xgi_oprom.c
-
-endif

src/northbridge/dmp/vortex86ex/chip.h

@@ -1,22 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 DMP Electronics Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef _NORTHBRIDGE_DMP_VORTEX86EX
-#define _NORTHBRIDGE_DMP_VORTEX86EX
-
-struct northbridge_dmp_vortex86ex_config {
-};
-
-#endif				/* _NORTHBRIDGE_DMP_VORTEX86EX */

src/soc/dmp/vortex86ex/Kconfig

@@ -13,7 +13,8 @@
 ## GNU General Public License for more details.
 ##
 
-config SOUTHBRIDGE_DMP_VORTEX86EX
+config SOC_DMP_VORTEX86EX
 	bool
+	select LATE_CBMEM_INIT
 	select AZALIA_PLUGIN_SUPPORT
 	select HAVE_HARD_RESET

src/soc/dmp/vortex86ex/Makefile.inc

@@ -13,7 +13,10 @@
 ## GNU General Public License for more details.
 ##
 
-ifeq ($(CONFIG_SOUTHBRIDGE_DMP_VORTEX86EX),y)
+ifeq ($(CONFIG_SOC_DMP_VORTEX86EX),y)
+
+ramstage-y += northbridge.c
+ramstage-y += xgi_oprom.c
 
 ramstage-y += southbridge.c
 ramstage-y += hard_reset.c

src/soc/dmp/vortex86ex/chip.h

@@ -13,10 +13,10 @@
  * GNU General Public License for more details.
  */
 
-#ifndef _SOUTHBRIDGE_DMP_VORTEX86EX
-#define _SOUTHBRIDGE_DMP_VORTEX86EX
+#ifndef _SOC_DMP_VORTEX86EX
+#define _SOC_DMP_VORTEX86EX
 
-struct southbridge_dmp_vortex86ex_config {
+struct soc_dmp_vortex86ex_config {
 	/* PCI function enables */
 	/* i.e. so that pci scan bus will find them. */
 	/* I am putting in IDE as an example but obviously this needs
@@ -31,4 +31,4 @@ struct southbridge_dmp_vortex86ex_config {
 	int enable_nvram;
 };
 
-#endif				/* _SOUTHBRIDGE_DMP_VORTEX86EX */
+#endif				/* _SOC_DMP_VORTEX86EX */