soc/intel/cache_as_ram.S: Fix CAR issues with Bootguard

It looks like the 'clear_car' code does not properly fill the required
cachelines so add code to fill cachelines explicitly.

Change-Id: Id5d77295f6d24f9d2bc23f39f8772fd172ac8910
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55791
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christopher Meis <christopher.meis@9elements.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

src/soc/intel/common/block/cpu/car/cache_as_ram.S

@@ -221,6 +221,23 @@ setup_car_mtrr:
 	is_bootguard_nem
 	jz	no_bootguard_car_continue
 
+	/*
+	 * With Bootguard some RO caching of the flash is already set up by
+	 * the ACM. It looks like in such a setup 'clear_car' will not properly fill
+	 * the cachelines. Fill all the CAR cachelines explicitly using sfence.
+	 * This assumes 64 bytes cachelines.
+	 */
+	movl	$CONFIG_DCACHE_RAM_BASE, %edi
+	movl	$CONFIG_DCACHE_RAM_SIZE, %ecx
+	shr	$0x06, %ecx
+	xor	%eax, %eax
+
+1:
+	movl	%eax, (%edi)
+	sfence
+	add	$64, %edi
+	loop	1b
+
 	clear_car
 
 	jmp	car_init_done