tegra124: nyan: Keep in memory structures below 4GB.

We'd been putting some data structures like the framebuffer and the cbmem at
the end of memory, but that may not actually be addressable as identity mapped
memory. This change clamps the addresses those structures are placed at so
they stay below 4GB.

BUG=None
TEST=Booted on nyan. Went into recovery mode and verified that there was a
recovery screen. Forced memory size to be 4GB and verified that the recovery
screen still shows up.
BRANCH=None

Original-Change-Id: I9e6b28212c113107d4f480b3dd846dd2349b3a91
Original-Signed-off-by: Gabe Black <gabeblack@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/185571
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Commit-Queue: Gabe Black <gabeblack@chromium.org>
Original-Tested-by: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit 63ea1274a838dc739d302d7551f1db42034c5bd0)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I970c1285270cb648bc67fa114d44c0841eab1615
Reviewed-on: http://review.coreboot.org/7397
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)

src/mainboard/google/nyan/romstage.c

@@ -71,7 +71,6 @@ static void configure_l2actlr(void)
 
 static void __attribute__((noinline)) romstage(void)
 {
-	int dram_size_mb;
 #if CONFIG_COLLECT_TIMESTAMPS
 	uint64_t romstage_start_time = timestamp_get();
 #endif
@@ -84,15 +83,14 @@ static void __attribute__((noinline)) romstage(void)
 
 	sdram_init(get_sdram_config());
 
-	/* used for MMU and CBMEM setup */
+	/* used for MMU and CBMEM setup, in MB */
-	dram_size_mb = sdram_size_mb();
-
 	u32 dram_start = (CONFIG_SYS_SDRAM_BASE >> 20);
-	u32 dram_end = dram_start + dram_size_mb;	/* plus one... */
+	u32 dram_end = sdram_max_addressable_mb();	/* plus one... */
+	u32 dram_size = dram_end - dram_start;
 
 	mmu_init();
 	mmu_config_range(0, dram_start, DCACHE_OFF);
-	mmu_config_range(dram_start, dram_size_mb, DCACHE_WRITEBACK);
+	mmu_config_range(dram_start, dram_size, DCACHE_WRITEBACK);
 	mmu_config_range(CONFIG_DRAM_DMA_START >> 20,
 			 CONFIG_DRAM_DMA_SIZE >> 20, DCACHE_OFF);
 	mmu_config_range(dram_end, 4096 - dram_end, DCACHE_OFF);

src/mainboard/google/nyan_big/romstage.c

@@ -71,7 +71,6 @@ static void configure_l2actlr(void)
 
 static void __attribute__((noinline)) romstage(void)
 {
-	int dram_size_mb;
 #if CONFIG_COLLECT_TIMESTAMPS
 	uint64_t romstage_start_time = timestamp_get();
 #endif
@@ -84,15 +83,14 @@ static void __attribute__((noinline)) romstage(void)
 
 	sdram_init(get_sdram_config());
 
-	/* used for MMU and CBMEM setup */
+	/* used for MMU and CBMEM setup, in MB */
-	dram_size_mb = sdram_size_mb();
-
 	u32 dram_start = (CONFIG_SYS_SDRAM_BASE >> 20);
-	u32 dram_end = dram_start + dram_size_mb;	/* plus one... */
+	u32 dram_end = sdram_max_addressable_mb();	/* plus one... */
+	u32 dram_size = dram_end - dram_start;
 
 	mmu_init();
 	mmu_config_range(0, dram_start, DCACHE_OFF);
-	mmu_config_range(dram_start, dram_size_mb, DCACHE_WRITEBACK);
+	mmu_config_range(dram_start, dram_size, DCACHE_WRITEBACK);
 	mmu_config_range(CONFIG_DRAM_DMA_START >> 20,
 			 CONFIG_DRAM_DMA_SIZE >> 20, DCACHE_OFF);
 	mmu_config_range(dram_end, 4096 - dram_end, DCACHE_OFF);

src/soc/nvidia/tegra124/cbmem.c

@@ -23,6 +23,5 @@
 
 void *cbmem_top(void)
 {
-	return (void *)(CONFIG_SYS_SDRAM_BASE +
+	return (void *)((sdram_max_addressable_mb() - FB_SIZE_MB) << 20UL);
-		((sdram_size_mb() - FB_SIZE_MB)<< 20UL));
 }

src/soc/nvidia/tegra124/display.c

@@ -228,7 +228,7 @@ static void update_window(struct display_controller *dc,
 
 uint32_t fb_base_mb(void)
 {
-	return CONFIG_SYS_SDRAM_BASE/MiB + (sdram_size_mb() - FB_SIZE_MB);
+	return sdram_max_addressable_mb() - FB_SIZE_MB;
 }
 
 /* this is really aimed at the lcd panel. That said, there are two display

src/soc/nvidia/tegra124/sdram.c

@@ -22,6 +22,7 @@
 #include <delay.h>
 #include <soc/addressmap.h>
 #include <soc/clock.h>
+#include <stdlib.h>
 
 #include "emc.h"
 #include "mc.h"
@@ -639,3 +640,8 @@ int sdram_size_mb(void)
 	printk(BIOS_DEBUG, "%s: Total SDRAM (MB): %u\n", __func__, total_size);
 	return total_size;
 }
+
+uintptr_t sdram_max_addressable_mb(void)
+{
+	return MIN((CONFIG_SYS_SDRAM_BASE/MiB) + sdram_size_mb(), 4096);
+}

src/soc/nvidia/tegra124/sdram.h

@@ -25,6 +25,7 @@
 uint32_t sdram_get_ram_code(void);
 void sdram_init(const struct sdram_params *param);
 int sdram_size_mb(void);
+uintptr_t sdram_max_addressable_mb(void);
 
 /* Save params to PMC scratch registers for use by BootROM on LP0 resume. */
 void sdram_lp0_save_params(const struct sdram_params *sdram);

src/soc/nvidia/tegra124/soc.c

@@ -35,8 +35,15 @@ static void soc_enable(device_t dev)
 	unsigned long fb_size = FB_SIZE_MB;
 
 	ram_resource(dev, 0, CONFIG_SYS_SDRAM_BASE/KiB,
-		(sdram_size_mb() - fb_size)*KiB);
+		(sdram_max_addressable_mb() - fb_size)*KiB -
+		CONFIG_SYS_SDRAM_BASE/KiB);
 	mmio_resource(dev, 1, lcdbase*KiB, fb_size*KiB);
+
+	u32 sdram_end_mb = sdram_size_mb() + CONFIG_SYS_SDRAM_BASE/MiB;
+
+	if (sdram_end_mb > sdram_max_addressable_mb())
+		ram_resource(dev, 2, sdram_max_addressable_mb()*KiB,
+			(sdram_end_mb - sdram_max_addressable_mb())*KiB);
 }
 
 static void soc_init(device_t dev)