soc/cavium/cn81xx: Use ATF from blobs repo
Use precompiled BL31 from blobs repo. There's no check for USE_BLOBS here as the included file is "free": The BL31 is Open-Source and licensed under BSD. Change-Id: I7e9eb429d11150d43aa070d1bd6a11ea71951ce3 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25751 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
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@ -17,6 +17,10 @@ config SOC_CAVIUM_CN81XX
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if SOC_CAVIUM_CN81XX
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if SOC_CAVIUM_CN81XX
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config ARM64_BL31_EXTERNAL_FILE
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string
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default "3rdparty/blobs/soc/cavium/cn81xx/bl31.elf"
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config ARCH_ARMV8_EXTENSION
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config ARCH_ARMV8_EXTENSION
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int
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int
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default 1
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default 1
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@ -65,9 +65,12 @@ ramstage-y += cpu.c
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ramstage-y += cpu_secondary.S
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ramstage-y += cpu_secondary.S
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ramstage-y += ecam0.c
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ramstage-y += ecam0.c
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ramstage-$(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE) += bl31_plat_params.c
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# BDK coreboot interface
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# BDK coreboot interface
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ramstage-y += ../common/bdk-coreboot.c
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ramstage-y += ../common/bdk-coreboot.c
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BL31_MAKEARGS += PLAT=t81 M0_CROSS_COMPILE="$(CROSS_COMPILE_arm)" ENABLE_SPE_FOR_LOWER_ELS=0
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CPPFLAGS_common += -Isrc/soc/cavium/cn81xx/include
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CPPFLAGS_common += -Isrc/soc/cavium/cn81xx/include
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@ -22,6 +22,8 @@ static struct bl31_plat_param *plat_params;
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void register_bl31_param(struct bl31_plat_param *param)
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void register_bl31_param(struct bl31_plat_param *param)
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{
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{
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ASSERT(param);
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param->next = plat_params;
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param->next = plat_params;
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plat_params = param;
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plat_params = param;
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}
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}
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@ -0,0 +1,44 @@
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/*
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* Copyright (c) 2018 Facebook Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __PLAT_PARAMS_H__
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#define __PLAT_PARAMS_H__
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#include <stdint.h>
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/* param type */
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enum {
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PARAM_NONE = 0,
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PARAM_FDT,
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PARAM_COREBOOT_TABLE,
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};
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/* common header for all plat parameter type */
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struct bl31_plat_param {
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uint64_t type;
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void *next;
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};
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struct bl31_fdt_param {
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struct bl31_plat_param h;
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uint64_t fdt_ptr;
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};
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struct bl31_u64_param {
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struct bl31_plat_param h;
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uint64_t value;
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};
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void params_early_setup(void *ptr);
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#endif /* __PLAT_PARAMS_H__ */
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@ -17,8 +17,7 @@
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#ifndef __BL31_PLAT_PARAMS_H__
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#ifndef __BL31_PLAT_PARAMS_H__
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#define __BL31_PLAT_PARAMS_H__
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#define __BL31_PLAT_PARAMS_H__
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// FIXME: use correct path one ATF is upstream
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#include <atf/plat_params.h>
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#include <arm-trusted-firmware/plat/rockchip/common/include/plat_params.h>
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void register_bl31_param(struct bl31_plat_param *param);
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void register_bl31_param(struct bl31_plat_param *param);
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@ -21,8 +21,11 @@
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SECTIONS
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SECTIONS
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{
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{
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DRAM_START(0x00000000)
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DRAM_START(0x00000000)
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/* FIXME: Place BL31 in first 1MiB */
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/* Secure region 0 - 1MiB */
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REGION(bl31, 0, 0xe0000, 0x1000)
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REGION(sff8104, 0xe0000, 0x20000, 0x1000)
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/* Insecure region 1MiB - TOP OF DRAM */
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/* bootblock-custom.S does setup CAR from SRAM_START to SRAM_END */
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/* bootblock-custom.S does setup CAR from SRAM_START to SRAM_END */
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SRAM_START(BOOTROM_OFFSET)
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SRAM_START(BOOTROM_OFFSET)
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STACK(BOOTROM_OFFSET, 16K)
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STACK(BOOTROM_OFFSET, 16K)
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@ -37,7 +37,10 @@
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#include <libbdk-hal/bdk-qlm.h>
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#include <libbdk-hal/bdk-qlm.h>
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#include <libbdk-hal/bdk-config.h>
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#include <libbdk-hal/bdk-config.h>
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#include <libbdk-arch/bdk-csrs-bgx.h>
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#include <libbdk-arch/bdk-csrs-bgx.h>
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#include <bootmem.h>
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#include <soc/bl31_plat_params.h>
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#include <cbfs.h>
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#include <cbmem.h>
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#include <fit.h>
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#include <fit.h>
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static const char *QLM_BGX_MODE_MAP[BDK_QLM_MODE_LAST] = {
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static const char *QLM_BGX_MODE_MAP[BDK_QLM_MODE_LAST] = {
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@ -289,18 +292,62 @@ static int dt_platform_fixup(struct device_tree_fixup *fixup,
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return 0;
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return 0;
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}
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}
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extern u8 _bl31[];
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extern u8 _ebl31[];
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extern u8 _sff8104[];
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extern u8 _esff8104[];
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void bootmem_platform_add_ranges(void)
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{
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/* ATF reserved */
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bootmem_add_range((uintptr_t)_bl31,
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((uintptr_t)_ebl31 - (uintptr_t)_bl31),
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BM_MEM_RESERVED);
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bootmem_add_range((uintptr_t)_sff8104,
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((uintptr_t)_esff8104 - (uintptr_t)_sff8104),
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BM_MEM_RESERVED);
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/* Scratchpad for ATF SATA quirks */
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bootmem_add_range(sdram_size_mb() * KiB, 1 * MiB, BM_MEM_RESERVED);
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}
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static void soc_read_resources(device_t dev)
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static void soc_read_resources(device_t dev)
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{
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{
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ram_resource(dev, 0, (uintptr_t)_dram / KiB, sdram_size_mb() * KiB);
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ram_resource(dev, 0, (uintptr_t)_dram / KiB, sdram_size_mb() * KiB);
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}
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}
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static void soc_init_atf(void)
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{
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static struct bl31_fdt_param fdt_param = {
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.h = { .type = PARAM_FDT, },
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};
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size_t size = 0;
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void *ptr = cbfs_boot_map_with_leak("sff8104-linux.dtb",
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CBFS_TYPE_RAW, &size);
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if (ptr)
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memcpy(_sff8104, ptr, size);
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/* Point to devicetree in secure memory */
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fdt_param.fdt_ptr = (uintptr_t)_sff8104;
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register_bl31_param(&fdt_param.h);
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static struct bl31_u64_param cbtable_param = {
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.h = { .type = PARAM_COREBOOT_TABLE, },
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};
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/* Point to coreboot tables */
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cbtable_param.value = (uint64_t)cbmem_find(CBMEM_ID_CBTABLE);
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if (cbtable_param.value)
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register_bl31_param(&cbtable_param.h);
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}
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static void soc_init(device_t dev)
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static void soc_init(device_t dev)
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{
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{
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/* Init ECAM, MDIO, PEM, PHY, QLM ... */
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/* Init ECAM, MDIO, PEM, PHY, QLM ... */
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bdk_boot();
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bdk_boot();
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/* TODO: additional trustzone init */
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if (IS_ENABLED(CONFIG_PAYLOAD_FIT_SUPPORT)) {
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if (IS_ENABLED(CONFIG_PAYLOAD_FIT_SUPPORT)) {
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struct device_tree_fixup *dt_fixup;
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struct device_tree_fixup *dt_fixup;
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&device_tree_fixups);
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&device_tree_fixups);
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}
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}
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}
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}
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if (IS_ENABLED(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE))
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soc_init_atf();
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}
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}
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static void soc_final(device_t dev)
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static void soc_final(device_t dev)
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@ -4,8 +4,7 @@ config SOC_CAVIUM_COMMON
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select BOOTBLOCK_CUSTOM
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select BOOTBLOCK_CUSTOM
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select CAVIUM_BDK
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select CAVIUM_BDK
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select FLATTENED_DEVICE_TREE
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select FLATTENED_DEVICE_TREE
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# FIXME: No Cavium support in ATF
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select ARM64_USE_ARM_TRUSTED_FIRMWARE
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# select ARM64_USE_ARM_TRUSTED_FIRMWARE
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if SOC_CAVIUM_COMMON
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if SOC_CAVIUM_COMMON
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@ -29,7 +29,6 @@ romstage-y += bdk-coreboot.c
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# ramstage
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# ramstage
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ramstage-y += cbmem.c
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ramstage-y += cbmem.c
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ramstage-$(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE) += bl31_plat_params.c
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CPPFLAGS_common += -Isrc/soc/cavium/common/include
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CPPFLAGS_common += -Isrc/soc/cavium/common/include
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