soc/intel/tigerlake: Generate LP4x SPD files using gen_spd.go

This change uses gen_spd.go and global_lp4x_mem_parts.json.txt to
generate SPD files for currently known LP4x memory parts that can be
used with TGL-based mainboards.

Following files are added:
1. spd-*.hex: SPD files auto-generated by gen_spd.go
2. spd_manifest.generated.txt: Manifest file auto-generated by
gen_spd.go

Mainboards can use the SPD files from SoC directly when creating SPD
binary to add to CBFS.

BUG=b:147321551,b:155239397

Change-Id: Ic3935e4f6d106cbdf496fdfa28a0991e2d238fd9
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41875
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This commit is contained in:
Furquan Shaikh 2020-05-29 08:56:58 -07:00 committed by Patrick Georgi
parent 4bd95295f1
commit 5ce3bca1e7
6 changed files with 169 additions and 0 deletions

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H9HCNNNBKMMLXR-NEE,spd-1.hex
H9HCNNNFAMMLXR-NEE,spd-2.hex
K4U6E3S4AA-MGCL,spd-1.hex
K4UBE3D4AA-MGCL,spd-3.hex
MT53E1G32D2NP-046 WT:A,spd-4.hex
H9HKNNNCRMBVAR-NEH,spd-1.hex
MT53E1G64D4SQ-046 WT:A,spd-4.hex
MT53E512M32D2NP-046 WT:F,spd-1.hex
NT6AP256T32AV-J2,spd-5.hex