From 5cf5828c02f1a10421417c63a5cd26bfa125a932 Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Wed, 18 Nov 2015 16:36:40 -0700 Subject: [PATCH] fsp1_0: Remove hardcoded microcode locations These are no longer needed. Test: Booted minnowmax. Change-Id: Ie77040f3506464c614760bd4d30280c8113373bd Signed-off-by: Martin Roth Reviewed-on: http://review.coreboot.org/12468 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer Reviewed-by: Alexandru Gagniuc --- src/cpu/intel/fsp_model_406dx/Kconfig | 5 ----- src/soc/intel/fsp_baytrail/Kconfig | 4 ---- 2 files changed, 9 deletions(-) diff --git a/src/cpu/intel/fsp_model_406dx/Kconfig b/src/cpu/intel/fsp_model_406dx/Kconfig index 30e7e592bc..c36851d485 100644 --- a/src/cpu/intel/fsp_model_406dx/Kconfig +++ b/src/cpu/intel/fsp_model_406dx/Kconfig @@ -53,11 +53,6 @@ config ENABLE_VMX bool "Enable VMX for virtualization" default n -config CPU_MICROCODE_CBFS_LOC - hex - depends on SUPPORT_CPU_UCODE_IN_CBFS - default 0xfff60040 - config HAVE_CPU_MICROCODE_FILE bool "Add microcode file" help diff --git a/src/soc/intel/fsp_baytrail/Kconfig b/src/soc/intel/fsp_baytrail/Kconfig index ff233083d4..2325d75838 100644 --- a/src/soc/intel/fsp_baytrail/Kconfig +++ b/src/soc/intel/fsp_baytrail/Kconfig @@ -86,10 +86,6 @@ config VGA_BIOS_ID This is the default PCI ID for the Bay Trail graphics devices. This string names the vbios ROM in cbfs. -config CPU_MICROCODE_CBFS_LOC - hex - default 0xfff10040 - config ENABLE_BUILTIN_COM1 bool "Enable built-in legacy Serial Port" help