src: Include <stdint.h> instead of <inttypes.h>

The <inttypes.h> header currently does nothing but include the
definitions from <stdint.h>, so let's #include that directly instead.

Change-Id: I9d83ad37d0d7300a093001596ce3f0b3830c5701
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34800
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>

src/cpu/amd/family_10h-family_15h/fidvid.c

@@ -92,7 +92,7 @@ b.-  prep_fid_change(...)
 #include <console/console.h>
 #include <cpu/amd/msr.h>
 #include <device/pci_ops.h>
-#include <inttypes.h>
+#include <stdint.h>
 #include <northbridge/amd/amdht/AsPsDefs.h>
 
 static inline void print_debug_fv(const char *str, u32 val)

src/drivers/intel/fsp2_0/hand_off_block.c

@@ -16,7 +16,7 @@
 #include <console/console.h>
 #include <fsp/api.h>
 #include <fsp/util.h>
-#include <inttypes.h>
+#include <stdint.h>
 #include <string.h>
 
 #define HOB_HEADER_LEN		8

src/drivers/uart/pl011.h

@@ -10,7 +10,7 @@
 #ifndef __DRIVERS_UART_PL011_H
 #define __DRIVERS_UART_PL011_H
 
-#include <inttypes.h>
+#include <stdint.h>
 #include <types.h>
 
 /* PL011 r1p5 registers */

src/drivers/vpd/vpd_tables.h

@@ -9,7 +9,7 @@
 #ifndef __LIB_VPD_TABLES_H__
 #define __LIB_VPD_TABLES_H__
 
-#include <inttypes.h>
+#include <stdint.h>
 
 #define VPD_ENTRY_MAGIC    "_SM_"
 #define VPD_INFO_MAGIC     \

src/lib/primitive_memtest.c

@@ -13,7 +13,7 @@
  * GNU General Public License for more details.
  */
 
-#include <inttypes.h>
+#include <stdint.h>
 #include <lib.h>
 #include <console/console.h>
 

src/northbridge/amd/amdfam10/amdfam10.h

@@ -17,7 +17,7 @@
 #ifndef AMDFAM10_H
 #define AMDFAM10_H
 
-#include <inttypes.h>
+#include <stdint.h>
 #include <device/device.h>
 #include "early_ht.h"
 

src/northbridge/amd/amdfam10/debug.h

@@ -16,7 +16,7 @@
 #ifndef AMDFAM10_DEBUG_H
 #define AMDFAM10_DEBUG_H
 
-#include <inttypes.h>
+#include <stdint.h>
 #include "pci.h"
 
 void print_debug_addr(const char *str, void *val);

src/northbridge/amd/amdfam10/early_ht.c

@@ -14,7 +14,7 @@
  */
 
 #include "early_ht.h"
-#include <inttypes.h>
+#include <stdint.h>
 #include <device/pci_ops.h>
 #include <device/pci_def.h>
 

src/northbridge/amd/amdfam10/pci.h

@@ -16,7 +16,7 @@
 #ifndef AMDFAM10_PCI_H
 #define AMDFAM10_PCI_H
 
-#include <inttypes.h>
+#include <stdint.h>
 #include <device/pci_type.h>
 #include <device/pci_def.h>
 

src/northbridge/amd/amdfam10/raminit_amdmct.c

@@ -15,7 +15,7 @@
  * GNU General Public License for more details.
  */
 
-#include <inttypes.h>
+#include <stdint.h>
 #include <arch/acpi.h>
 #include <arch/cpu.h>
 #include <device/pci.h>

src/northbridge/amd/amdfam10/setup_resource_map.c

@@ -15,7 +15,7 @@
  */
 
 #include <arch/io.h>
-#include <inttypes.h>
+#include <stdint.h>
 #include <console/console.h>
 #include <device/pci_ops.h>
 #include <northbridge/amd/amdfam10/raminit.h>

src/northbridge/amd/amdht/comlib.h

@@ -17,7 +17,7 @@
 #define COMLIB_H
 
 #include <assert.h>
-#include <inttypes.h>
+#include <stdint.h>
 #include <stdlib.h>
 #include "porting.h"
 

src/northbridge/amd/amdht/h3ncmn.h

@@ -17,7 +17,7 @@
 #ifndef H3NCMN_H
 #define H3NCMN_H
 
-#include <inttypes.h>
+#include <stdint.h>
 #include <device/pci.h>
 #include <cpu/amd/msr.h>
 

src/northbridge/amd/amdht/ht_wrapper.h

@@ -18,7 +18,7 @@
 
 #include <northbridge/amd/amdfam10/raminit.h>
 #include <northbridge/amd/amdfam10/amdfam10.h>
-#include <inttypes.h>
+#include <stdint.h>
 #include "h3finit.h"
 
 void amd_ht_fixup(struct sys_info *sysinfo);

src/northbridge/amd/amdmct/mct/mct_d.h

@@ -22,7 +22,7 @@
 
 #define DQS_TRAIN_DEBUG 0
 
-#include <inttypes.h>
+#include <stdint.h>
 #include <northbridge/amd/amdfam10/debug.h>
 #include <northbridge/amd/amdfam10/raminit.h>
 

src/northbridge/amd/amdmct/mct/mct_d_gcc.h

@@ -16,7 +16,7 @@
 #ifndef MCT_D_GCC_H
 #define MCT_D_GCC_H
 
-#include <inttypes.h>
+#include <stdint.h>
 
 void _WRMSR(u32 addr, u32 lo, u32 hi);
 void _RDMSR(u32 addr, u32 *lo, u32 *hi);

src/northbridge/amd/amdmct/mct/mctardk3.c

@@ -13,7 +13,7 @@
  * GNU General Public License for more details.
  */
 
-#include <inttypes.h>
+#include <stdint.h>
 #include "mct_d.h"
 
 static void Get_ChannelPS_Cfg0_D(u8 MAAdimms, u8 Speed, u8 MAAload,

src/northbridge/amd/amdmct/mct/mctardk4.c

@@ -13,7 +13,7 @@
  * GNU General Public License for more details.
  */
 
-#include <inttypes.h>
+#include <stdint.h>
 #include "mct_d.h"
 
 static void Get_ChannelPS_Cfg0_D(u8 MAAdimms, u8 Speed, u8 MAAload,

src/northbridge/amd/amdmct/mct_ddr3/mct_d.h

@@ -22,7 +22,7 @@
 
 #define DQS_TRAIN_DEBUG 0
 
-#include <inttypes.h>
+#include <stdint.h>
 #include <northbridge/amd/amdfam10/raminit.h>
 
 /*===========================================================================

src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.c

@@ -15,7 +15,7 @@
  */
 
 #include "mct_d_gcc.h"
-#include <inttypes.h>
+#include <stdint.h>
 #include <arch/cpu.h>
 
 void _WRMSR(u32 addr, u32 lo, u32 hi)

src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.h

@@ -17,7 +17,7 @@
 #ifndef MCT_D_GCC_H
 #define MCT_D_GCC_H
 
-#include <inttypes.h>
+#include <stdint.h>
 #include <cpu/x86/cr.h>
 
 void _WRMSR(u32 addr, u32 lo, u32 hi);

src/northbridge/amd/amdmct/mct_ddr3/mctardk5.c

@@ -17,7 +17,7 @@
 /* AM3/ASB2/C32/G34 DDR3 */
 
 #include <arch/cpu.h>
-#include <inttypes.h>
+#include <stdint.h>
 #include "mct_d.h"
 #include "mct_d_gcc.h"
 

src/northbridge/amd/amdmct/mct_ddr3/mctchi_d.c

@@ -13,7 +13,7 @@
  * GNU General Public License for more details.
  */
 
-#include <inttypes.h>
+#include <stdint.h>
 #include "mct_d.h"
 #include "mct_d_gcc.h"
 #include <console/console.h>

src/northbridge/amd/amdmct/mct_ddr3/mctcsi_d.c

@@ -20,7 +20,7 @@
  * ;page size), and subtract 8.
  */
 
-#include <inttypes.h>
+#include <stdint.h>
 #include "mct_d.h"
 #include "mct_d_gcc.h"
 #include <console/console.h>

src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c

@@ -14,7 +14,7 @@
  * GNU General Public License for more details.
  */
 
-#include <inttypes.h>
+#include <stdint.h>
 #include <console/console.h>
 #include <cpu/x86/cr.h>
 #include <string.h>

src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c

@@ -15,7 +15,7 @@
  */
 
 #include <arch/cpu.h>
-#include <inttypes.h>
+#include <stdint.h>
 #include <console/console.h>
 #include <device/pci_ops.h>
 

src/northbridge/amd/amdmct/mct_ddr3/mcthdi.c

@@ -14,7 +14,7 @@
  * GNU General Public License for more details.
  */
 
-#include <inttypes.h>
+#include <stdint.h>
 #include "mct_d.h"
 #include "mct_d_gcc.h"
 

src/northbridge/amd/amdmct/mct_ddr3/mcthwl.c

@@ -15,7 +15,7 @@
  */
 
 #include <arch/cpu.h>
-#include <inttypes.h>
+#include <stdint.h>
 #include <console/console.h>
 #include <string.h>
 #include "mct_d.h"

src/northbridge/amd/amdmct/mct_ddr3/mctmtr_d.c

@@ -14,7 +14,7 @@
  * GNU General Public License for more details.
  */
 
-#include <inttypes.h>
+#include <stdint.h>
 #include <console/console.h>
 #include <cpu/amd/mtrr.h>
 #include <cpu/x86/mtrr.h>

src/northbridge/amd/amdmct/mct_ddr3/mctndi_d.c

@@ -14,7 +14,7 @@
  * GNU General Public License for more details.
  */
 
-#include <inttypes.h>
+#include <stdint.h>
 #include <console/console.h>
 
 #include "mct_d.h"

src/northbridge/amd/amdmct/mct_ddr3/mctprob.c

@@ -13,7 +13,7 @@
  * GNU General Public License for more details.
  */
 
-#include <inttypes.h>
+#include <stdint.h>
 
 #include "mct_d.h"
 #include "mct_d_gcc.h"

src/northbridge/amd/amdmct/mct_ddr3/mctproc.c

@@ -14,7 +14,7 @@
  * GNU General Public License for more details.
  */
 
-#include <inttypes.h>
+#include <stdint.h>
 
 #include "mct_d.h"
 #include "mct_d_gcc.h"

src/northbridge/amd/amdmct/mct_ddr3/mctprod.c

@@ -14,7 +14,7 @@
  * GNU General Public License for more details.
  */
 
-#include <inttypes.h>
+#include <stdint.h>
 
 #include "mct_d.h"
 #include "mct_d_gcc.h"

src/northbridge/amd/amdmct/mct_ddr3/mctrci.c

@@ -15,7 +15,7 @@
  */
 
 #include <arch/cpu.h>
-#include <inttypes.h>
+#include <stdint.h>
 #include <console/console.h>
 
 #include "mct_d.h"

src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c

@@ -15,7 +15,7 @@
  */
 
 #include <arch/cpu.h>
-#include <inttypes.h>
+#include <stdint.h>
 #include <console/console.h>
 
 #include "mct_d.h"

src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c

@@ -20,7 +20,7 @@
 ******************************************************************************/
 
 #include <arch/cpu.h>
-#include <inttypes.h>
+#include <stdint.h>
 #include <console/console.h>
 #include <cpu/x86/cr.h>
 #include <string.h>

src/northbridge/amd/amdmct/mct_ddr3/mctsrc1p.c

@@ -15,7 +15,7 @@
  */
 
 #include <arch/cpu.h>
-#include <inttypes.h>
+#include <stdint.h>
 
 #include "mct_d.h"
 #include "mct_d_gcc.h"

src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c

@@ -18,7 +18,7 @@
  * Description: Max Read Latency Training feature for DDR 3 MCT
  */
 
-#include <inttypes.h>
+#include <stdint.h>
 #include <console/console.h>
 #include <cpu/amd/msr.h>
 #include <cpu/x86/cr.h>

src/northbridge/amd/amdmct/mct_ddr3/mctwl.c

@@ -15,7 +15,7 @@
  */
 
 #include <arch/cpu.h>
-#include <inttypes.h>
+#include <stdint.h>
 #include <console/console.h>
 
 #include "mct_d.h"

src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c

@@ -14,7 +14,7 @@
  * GNU General Public License for more details.
  */
 
-#include <inttypes.h>
+#include <stdint.h>
 #include <console/console.h>
 #include <northbridge/amd/amdfam10/amdfam10.h>
 

src/northbridge/amd/amdmct/mct_ddr3/modtrd.c

@@ -13,7 +13,7 @@
  * GNU General Public License for more details.
  */
 
-#include <inttypes.h>
+#include <stdint.h>
 
 #include "mct_d.h"
 #include "mct_d_gcc.h"

src/northbridge/amd/amdmct/mct_ddr3/modtrdim.c

@@ -16,7 +16,7 @@
 
 /* This file contains functions for odt setting on registered DDR3 dimms */
 
-#include <inttypes.h>
+#include <stdint.h>
 #include <console/console.h>
 
 #include "mct_d.h"

src/northbridge/amd/amdmct/mct_ddr3/mport_d.c

@@ -14,7 +14,7 @@
  */
 
 #include <arch/io.h>
-#include <inttypes.h>
+#include <stdint.h>
 
 #include "mct_d.h"
 #include "mct_d_gcc.h"

src/northbridge/amd/amdmct/mct_ddr3/mutilc_d.c

@@ -17,7 +17,7 @@
 /* This file contains functions for common utility functions */
 
 #include <arch/cpu.h>
-#include <inttypes.h>
+#include <stdint.h>
 
 #include "mct_d.h"
 #include "mct_d_gcc.h"

src/northbridge/amd/amdmct/mct_ddr3/s3utils.c

@@ -29,7 +29,7 @@
 #include <spi-generic.h>
 #include <spi_flash.h>
 #include <pc80/mc146818rtc.h>
-#include <inttypes.h>
+#include <stdint.h>
 #include <types.h>
 
 #include "mct_d.h"

src/northbridge/amd/amdmct/wrappers/mcti.h

@@ -18,7 +18,7 @@
 #ifndef MCTI_H
 #define MCTI_H
 
-#include <inttypes.h>
+#include <stdint.h>
 #include <stdlib.h>
 #include <pc80/mc146818rtc.h>
 

src/soc/cavium/cn81xx/include/soc/soc.h

@@ -16,7 +16,7 @@
 #ifndef __SOC_CAVIUM_CN81XX_INCLUDE_SOC_SOC_H
 #define __SOC_CAVIUM_CN81XX_INCLUDE_SOC_SOC_H
 
-#include <inttypes.h>
+#include <stdint.h>
 #include <types.h>
 
 /* MIO BOOT Registers */

src/soc/cavium/cn81xx/include/soc/timer.h

@@ -16,7 +16,7 @@
 #ifndef __SOC_CAVIUM_CN81XX_TIMER_H__
 #define __SOC_CAVIUM_CN81XX_TIMER_H__
 
-#include <inttypes.h>
+#include <stdint.h>
 #include <types.h>
 
 /* Watchdog functions */

src/soc/cavium/cn81xx/include/soc/uart.h

@@ -16,7 +16,7 @@
 #ifndef __SOC_CAVIUM_COMMON_INCLUDE_SOC_UART_H
 #define __SOC_CAVIUM_COMMON_INCLUDE_SOC_UART_H
 
-#include <inttypes.h>
+#include <stdint.h>
 #include <types.h>
 
 int uart_is_enabled(const size_t bus);

src/soc/cavium/cn81xx/timer.c

@@ -20,7 +20,6 @@
 #include <device/mmio.h>
 #include <arch/lib_helpers.h>
 #include <console/console.h>
-#include <inttypes.h>
 #include <soc/clock.h>
 #include <soc/timer.h>
 #include <stdint.h>

src/soc/nvidia/tegra124/dma.c

@@ -17,7 +17,7 @@
 
 #include <device/mmio.h>
 #include <console/console.h>
-#include <inttypes.h>
+#include <stdint.h>
 #include <soc/addressmap.h>
 #include <soc/dma.h>
 #include <stddef.h>

src/soc/nvidia/tegra124/include/soc/dma.h

@@ -18,7 +18,7 @@
 #ifndef __NVIDIA_TEGRA124_DMA_H__
 #define __NVIDIA_TEGRA124_DMA_H__
 
-#include <inttypes.h>
+#include <stdint.h>
 #include <soc/addressmap.h>
 
 /*

src/soc/nvidia/tegra124/spi.c

@@ -20,7 +20,7 @@
 #include <boot_device.h>
 #include <console/console.h>
 #include <delay.h>
-#include <inttypes.h>
+#include <stdint.h>
 #include <soc/addressmap.h>
 #include <soc/dma.h>
 #include <soc/spi.h>

src/soc/nvidia/tegra210/dma.c

@@ -17,7 +17,7 @@
 
 #include <device/mmio.h>
 #include <console/console.h>
-#include <inttypes.h>
+#include <stdint.h>
 #include <soc/addressmap.h>
 #include <soc/dma.h>
 #include <stddef.h>

src/soc/nvidia/tegra210/include/soc/dma.h

@@ -17,7 +17,7 @@
 #ifndef __NVIDIA_TEGRA210_DMA_H__
 #define __NVIDIA_TEGRA210_DMA_H__
 
-#include <inttypes.h>
+#include <stdint.h>
 #include <soc/addressmap.h>
 #include <types.h>
 

src/soc/nvidia/tegra210/spi.c

@@ -20,7 +20,7 @@
 #include <boot_device.h>
 #include <console/console.h>
 #include <delay.h>
-#include <inttypes.h>
+#include <stdint.h>
 #include <spi-generic.h>
 #include <spi_flash.h>
 #include <soc/addressmap.h>

src/soc/rockchip/rk3288/include/soc/timer.h

@@ -16,7 +16,7 @@
 #ifndef __SOC_ROCKCHIP_RK3288_TIMER_H__
 #define __SOC_ROCKCHIP_RK3288_TIMER_H__
 
-#include <inttypes.h>
+#include <stdint.h>
 #include <soc/addressmap.h>
 #include <soc/clock.h>
 #include <timer.h>

src/soc/rockchip/rk3399/include/soc/timer.h

@@ -16,7 +16,7 @@
 #ifndef __SOC_ROCKCHIP_RK3399_TIMER_H__
 #define __SOC_ROCKCHIP_RK3399_TIMER_H__
 
-#include <inttypes.h>
+#include <stdint.h>
 #include <soc/addressmap.h>
 #include <timer.h>
 

src/vendorcode/cavium/include/bdk/libbdk-hal/bdk-config.h

@@ -39,7 +39,7 @@
 * ARISING OUT OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
 ***********************license end**************************************/
 
-#include <inttypes.h>
+#include <stdint.h>
 #include <bdk-devicetree.h>
 
 /**