drivers/intel/gma: Fix undefined behavior
Fix undefined behavior found by clang's -Wshift-sign-overflow, find, and source inspection. Left shifting an int where the right operand is >= the width of the type is undefined. Add UL suffix since it's safe for unsigned types. Change-Id: I5240a19647c8ad59f64925f3e1c199446a886d2d Signed-off-by: Ryan Salsamendi <rsalsamendi@hotmail.com> Reviewed-on: https://review.coreboot.org/20466 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Ryan Salsamendi
Martin Roth
parent
3f2fe18965
commit
5d09d48050
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@ -33,7 +33,7 @@
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/* things that are, strangely, not defined anywhere? */
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#define PCH_PP_UNLOCK 0xabcd0000
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#define WMx_LP_SR_EN (1<<31)
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#define WMx_LP_SR_EN (1UL<<31)
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#define PRB0_TAIL 0x02030
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#define PRB0_HEAD 0x02034
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#define PRB0_START 0x02038
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@ -600,7 +600,7 @@
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#define FW_BLC 0x020d8
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#define FW_BLC2 0x020dc
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#define FW_BLC_SELF 0x020e0 /* 915+ only */
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#define FW_BLC_SELF_EN_MASK (1<<31)
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#define FW_BLC_SELF_EN_MASK (1UL<<31)
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#define FW_BLC_SELF_FIFO_MASK (1<<16) /* 945 only */
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#define FW_BLC_SELF_EN (1<<15) /* 945 only */
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#define MM_BURST_LENGTH 0x00700000
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@ -751,7 +751,7 @@
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#define FBC_CFB_BASE 0x03200 /* 4k page aligned */
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#define FBC_LL_BASE 0x03204 /* 4k page aligned */
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#define FBC_CONTROL 0x03208
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#define FBC_CTL_EN (1<<31)
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#define FBC_CTL_EN (1UL<<31)
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#define FBC_CTL_PERIODIC (1<<30)
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#define FBC_CTL_INTERVAL_SHIFT (16)
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#define FBC_CTL_UNCOMPRESSIBLE (1<<14)
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@ -761,7 +761,7 @@
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#define FBC_COMMAND 0x0320c
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#define FBC_CMD_COMPRESS (1<<0)
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#define FBC_STATUS 0x03210
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#define FBC_STAT_COMPRESSING (1<<31)
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#define FBC_STAT_COMPRESSING (1UL<<31)
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#define FBC_STAT_COMPRESSED (1<<30)
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#define FBC_STAT_MODIFIED (1<<29)
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#define FBC_STAT_CURRENT_LINE (1<<0)
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@ -782,7 +782,7 @@
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/* Framebuffer compression for GM45+ */
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#define DPFC_CB_BASE 0x3200
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#define DPFC_CONTROL 0x3208
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#define DPFC_CTL_EN (1<<31)
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#define DPFC_CTL_EN (1UL<<31)
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#define DPFC_CTL_PLANEA (0<<30)
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#define DPFC_CTL_PLANEB (1<<30)
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#define DPFC_CTL_FENCE_EN (1<<29)
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@ -805,7 +805,7 @@
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#define DPFC_STATUS2 0x3214
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#define DPFC_FENCE_YOFF 0x3218
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#define DPFC_CHICKEN 0x3224
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#define DPFC_HT_MODIFY (1<<31)
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#define DPFC_HT_MODIFY (1UL<<31)
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/* Framebuffer compression for Ironlake */
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#define ILK_DPFC_CB_BASE 0x43200
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@ -878,7 +878,7 @@
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#define GMBUS_NUM_PORTS (GMBUS_PORT_DPD - GMBUS_PORT_SSC + 1)
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#define GMBUS_PORT_MASK 7
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#define GMBUS1 0x5104 /* command/status */
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#define GMBUS_SW_CLR_INT (1<<31)
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#define GMBUS_SW_CLR_INT (1UL<<31)
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#define GMBUS_SW_RDY (1<<30)
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#define GMBUS_ENT (1<<29) /* enable timeout */
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#define GMBUS_CYCLE_NONE (0<<25)
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@ -906,7 +906,7 @@
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#define GMBUS_HW_WAIT_EN (1<<1)
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#define GMBUS_HW_RDY_EN (1<<0)
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#define GMBUS5 0x5120 /* byte index */
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#define GMBUS_2BYTE_INDEX_EN (1<<31)
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#define GMBUS_2BYTE_INDEX_EN (1UL<<31)
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/*
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* Clock control & power management
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@ -926,7 +926,7 @@
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#define _DPLL_A 0x06014
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#define _DPLL_B 0x06018
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#define DPLL(pipe) _PIPE(pipe, _DPLL_A, _DPLL_B)
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#define DPLL_VCO_ENABLE (1 << 31)
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#define DPLL_VCO_ENABLE (1UL << 31)
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#define DPLL_DVO_HIGH_SPEED (1 << 30)
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#define DPLL_EXT_BUFFER_ENABLE_VLV (1 << 30)
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#define DPLL_SYNCLOCK_ENABLE (1 << 29)
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@ -954,11 +954,11 @@
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#define PPCR_ON (1<<0)
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#define DVOB 0x61140
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#define DVOB_ON (1<<31)
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#define DVOB_ON (1UL<<31)
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#define DVOC 0x61160
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#define DVOC_ON (1<<31)
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#define DVOC_ON (1UL<<31)
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#define LVDS 0x61180
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#define LVDS_ON (1<<31)
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#define LVDS_ON (1UL<<31)
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#define LVDS_CLOCK_A_POWERUP_ALL (3 << 8)
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#define LVDS_CLOCK_B_POWERUP_ALL (3 << 4)
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#define LVDS_CLOCK_BOTH_POWERUP_ALL (3 << 2)
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@ -1301,7 +1301,7 @@
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#define PCH_ADPA 0xe1100
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#define VLV_ADPA (VLV_DISPLAY_BASE + ADPA)
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#define ADPA_DAC_ENABLE (1<<31)
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#define ADPA_DAC_ENABLE (1UL<<31)
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#define ADPA_DAC_DISABLE 0
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#define ADPA_PIPE_SELECT_MASK (1<<30)
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#define ADPA_PIPE_A_SELECT 0
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@ -1405,7 +1405,7 @@
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/* SDVO port control */
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#define SDVOB 0x61140
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#define SDVOC 0x61160
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#define SDVO_ENABLE (1 << 31)
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#define SDVO_ENABLE (1UL << 31)
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#define SDVO_PIPE_B_SELECT (1 << 30)
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#define SDVO_STALL_SELECT (1 << 29)
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#define SDVO_INTERRUPT_ENABLE (1 << 26)
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@ -1443,7 +1443,7 @@
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#define DVOA 0x61120
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#define DVOB 0x61140
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#define DVOC 0x61160
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#define DVO_ENABLE (1 << 31)
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#define DVO_ENABLE (1UL << 31)
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#define DVO_PIPE_B_SELECT (1 << 30)
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#define DVO_PIPE_STALL_UNUSED (0 << 28)
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#define DVO_PIPE_STALL (1 << 28)
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@ -1479,7 +1479,7 @@
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* Enables the LVDS port. This bit must be set before DPLLs are enabled, as
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* the DPLL semantics change when the LVDS is assigned to that pipe.
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*/
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#define LVDS_PORT_EN (1 << 31)
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#define LVDS_PORT_EN (1UL << 31)
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/* Selects pipe B for LVDS data. Must be set on pre-965. */
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#define LVDS_PIPEB_SELECT (1 << 30)
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#define LVDS_PIPE_MASK (1 << 30)
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@ -1531,7 +1531,7 @@
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#define VIDEO_DIP_DATA_SIZE 32
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#define VIDEO_DIP_CTL 0x61170
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/* Pre HSW: */
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#define VIDEO_DIP_ENABLE (1 << 31)
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#define VIDEO_DIP_ENABLE (1UL << 31)
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#define VIDEO_DIP_PORT_B (1 << 29)
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#define VIDEO_DIP_PORT_C (2 << 29)
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#define VIDEO_DIP_PORT_D (3 << 29)
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@ -1559,7 +1559,7 @@
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/* Panel power sequencing */
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#define PP_STATUS 0x61200
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#define PP_ON (1 << 31)
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#define PP_ON (1UL << 31)
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/*
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* Indicates that all dependencies of the panel are on:
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*
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@ -1592,7 +1592,7 @@
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/* Panel fitting */
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#define PFIT_CONTROL 0x61230
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#define PFIT_ENABLE (1 << 31)
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#define PFIT_ENABLE (1UL << 31)
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#define PFIT_PIPE_MASK (3 << 29)
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#define PFIT_PIPE_SHIFT 29
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#define VERT_INTERP_DISABLE (0 << 10)
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@ -1627,7 +1627,7 @@
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/* Backlight control */
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#define BLC_PWM_CTL2 0x61250 /* 965+ only */
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#define BLM_PWM_ENABLE (1 << 31)
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#define BLM_PWM_ENABLE (1UL << 31)
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#define BLM_COMBINATION_MODE (1 << 30) /* gen4 only */
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#define BLM_PIPE_SELECT (1 << 29)
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#define BLM_PIPE_SELECT_IVB (3 << 29)
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@ -1672,11 +1672,11 @@
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/* New registers for PCH-split platforms. Safe where new bits show up, the
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* register layout machtes with gen4 BLC_PWM_CTL[12]. */
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#define BLC_PWM_CPU_CTL2 0x48250
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#define BLC_PWM2_ENABLE (1<<31)
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#define BLC_PWM2_ENABLE (1UL<<31)
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#define BLC_PWM_CPU_CTL 0x48254
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#define BLM_HIST_CTL 0x48260
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#define ENH_HIST_ENABLE (1<<31)
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#define ENH_HIST_ENABLE (1UL<<31)
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#define ENH_MODIF_TBL_ENABLE (1<<30)
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#define ENH_PIPE_A_SELECT (0<<29)
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#define ENH_PIPE_B_SELECT (1<<29)
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@ -1692,7 +1692,7 @@
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#define BLM_HIST_ENH 0x48264
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#define BLM_HIST_GUARD_BAND 0x48268
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#define BLM_HIST_INTR_ENABLE (1<<31)
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#define BLM_HIST_INTR_ENABLE (1UL<<31)
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#define BLM_HIST_EVENT_STATUS (1<<30)
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#define BLM_HIST_INTR_DELAY_MASK (0xFF<<22)
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#define BLM_HIST_INTR_DELAY_SHIFT 22
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@ -1700,7 +1700,7 @@
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/* PCH CTL1 is totally different, all but the below bits are reserved. CTL2 is
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* like the normal CTL from gen4 and earlier. Hooray for confusing naming. */
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#define BLC_PWM_PCH_CTL1 0xc8250
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#define BLM_PCH_PWM_ENABLE (1 << 31)
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#define BLM_PCH_PWM_ENABLE (1UL << 31)
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#define BLM_PCH_OVERRIDE_ENABLE (1 << 30)
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#define BLM_PCH_POLARITY (1 << 29)
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#define BLC_PWM_PCH_CTL2 0xc8254
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@ -1708,7 +1708,7 @@
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/* TV port control */
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#define TV_CTL 0x68000
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/** Enables the TV encoder */
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# define TV_ENC_ENABLE (1 << 31)
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# define TV_ENC_ENABLE (1UL << 31)
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/** Sources the TV encoder input from pipe B instead of A. */
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# define TV_ENC_PIPEB_SELECT (1 << 30)
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/** Outputs composite video (DAC A only) */
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@ -1780,7 +1780,7 @@
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*
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* This gets cleared when TV_DAC_STATE_EN is cleared
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*/
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# define TVDAC_STATE_CHG (1 << 31)
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# define TVDAC_STATE_CHG (1UL << 31)
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# define TVDAC_SENSE_MASK (7 << 28)
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/** Reports that DAC A voltage is above the detect threshold */
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# define TVDAC_A_SENSE (1 << 30)
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@ -1907,7 +1907,7 @@
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#define TV_H_CTL_2 0x68034
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/** Enables the colorburst (needed for non-component color) */
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# define TV_BURST_ENA (1 << 31)
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# define TV_BURST_ENA (1UL << 31)
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/** Offset of the colorburst from the start of hsync, in pixels minus one. */
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# define TV_HBURST_START_SHIFT 16
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# define TV_HBURST_START_MASK 0x1fff0000
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@ -1952,7 +1952,7 @@
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#define TV_V_CTL_3 0x68044
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/** Enables generation of the equalization signal */
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# define TV_EQUAL_ENA (1 << 31)
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# define TV_EQUAL_ENA (1UL << 31)
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/** Length of vsync, in half lines */
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# define TV_VEQ_LEN_MASK 0x007f0000
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# define TV_VEQ_LEN_SHIFT 16
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@ -2026,7 +2026,7 @@
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#define TV_SC_CTL_1 0x68060
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/** Turns on the first subcarrier phase generation DDA */
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# define TV_SC_DDA1_EN (1 << 31)
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# define TV_SC_DDA1_EN (1UL << 31)
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/** Turns on the first subcarrier phase generation DDA */
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# define TV_SC_DDA2_EN (1 << 30)
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/** Turns on the first subcarrier phase generation DDA */
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@ -2089,7 +2089,7 @@
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* If set, the rest of the registers are ignored, and the calculated values can
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* be read back from the register.
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*/
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# define TV_AUTO_SCALE (1 << 31)
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# define TV_AUTO_SCALE (1UL << 31)
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/**
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* Disables the vertical filter.
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*
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@ -2152,7 +2152,7 @@
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# define TV_VSCALE_IP_FRAC_SHIFT 0
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#define TV_CC_CONTROL 0x68090
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# define TV_CC_ENABLE (1 << 31)
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# define TV_CC_ENABLE (1UL << 31)
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/**
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* Specifies which field to send the CC data in.
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*
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@ -2168,7 +2168,7 @@
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# define TV_CC_LINE_SHIFT 0
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#define TV_CC_DATA 0x68094
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# define TV_CC_RDY (1 << 31)
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# define TV_CC_RDY (1UL << 31)
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/** Second word of CC data to be transmitted. */
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# define TV_CC_DATA_2_MASK 0x007f0000
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# define TV_CC_DATA_2_SHIFT 16
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@ -2191,7 +2191,7 @@
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#define DP_C 0x64200
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#define DP_D 0x64300
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#define DP_PORT_EN (1 << 31)
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#define DP_PORT_EN (1UL << 31)
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#define DP_PIPEB_SELECT (1 << 30)
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#define DP_PIPE_MASK (1 << 30)
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@ -2301,7 +2301,7 @@
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#define DPD_AUX_CH_DATA4 0x64320
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#define DPD_AUX_CH_DATA5 0x64324
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#define DP_AUX_CH_CTL_SEND_BUSY (1 << 31)
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#define DP_AUX_CH_CTL_SEND_BUSY (1UL << 31)
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#define DP_AUX_CH_CTL_DONE (1 << 30)
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#define DP_AUX_CH_CTL_INTERRUPT (1 << 29)
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#define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28)
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@ -2380,7 +2380,7 @@
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#define DSL_LINEMASK_GEN2 0x00000fff
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#define DSL_LINEMASK_GEN3 0x00001fff
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#define _PIPEACONF 0x70008
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#define PIPECONF_ENABLE (1<<31)
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#define PIPECONF_ENABLE (1UL<<31)
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#define PIPECONF_DISABLE 0
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#define PIPECONF_DOUBLE_WIDE (1<<30)
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#define I965_PIPECONF_ACTIVE (1<<30)
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@ -2524,7 +2524,7 @@
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#define DSPFW_CURSORA_SHIFT 8
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#define DSPFW_PLANEC_MASK (0x7f)
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#define DSPFW3 0x7003c
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#define DSPFW_HPLL_SR_EN (1<<31)
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#define DSPFW_HPLL_SR_EN (1UL<<31)
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#define DSPFW_CURSOR_SR_SHIFT 24
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#define PINEVIEW_SELF_REFRESH_EN (1<<30)
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#define DSPFW_CURSOR_SR_MASK (0x3f<<24)
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@ -2536,14 +2536,14 @@
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#define DRAIN_LATENCY_PRECISION_32 32
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#define DRAIN_LATENCY_PRECISION_16 16
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#define VLV_DDL1 0x70050
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#define DDL_CURSORA_PRECISION_32 (1<<31)
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#define DDL_CURSORA_PRECISION_16 (0<<31)
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#define DDL_CURSORA_PRECISION_32 (1UL<<31)
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#define DDL_CURSORA_PRECISION_16 (0UL<<31)
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#define DDL_CURSORA_SHIFT 24
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#define DDL_PLANEA_PRECISION_32 (1<<7)
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#define DDL_PLANEA_PRECISION_16 (0<<7)
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#define VLV_DDL2 0x70054
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#define DDL_CURSORB_PRECISION_32 (1<<31)
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#define DDL_CURSORB_PRECISION_16 (0<<31)
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#define DDL_CURSORB_PRECISION_32 (1UL<<31)
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#define DDL_CURSORB_PRECISION_16 (0UL<<31)
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#define DDL_CURSORB_SHIFT 24
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#define DDL_PLANEB_PRECISION_32 (1<<7)
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#define DDL_PLANEB_PRECISION_16 (0<<7)
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@ -2592,7 +2592,7 @@
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#define WM0_PIPEB_ILK 0x45104
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#define WM0_PIPEC_IVB 0x45200
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#define WM1_LP_ILK 0x45108
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#define WM1_LP_SR_EN (1<<31)
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#define WM1_LP_SR_EN (1UL<<31)
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#define WM1_LP_LATENCY_SHIFT 24
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#define WM1_LP_LATENCY_MASK (0x7f<<24)
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#define WM1_LP_FBC_MASK (0xf<<20)
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@ -2601,13 +2601,13 @@
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#define WM1_LP_SR_SHIFT 8
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#define WM1_LP_CURSOR_MASK (0x3f)
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#define WM2_LP_ILK 0x4510c
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#define WM2_LP_EN (1<<31)
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#define WM2_LP_EN (1UL<<31)
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#define WM3_LP_ILK 0x45110
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#define WM3_LP_EN (1<<31)
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#define WM3_LP_EN (1UL<<31)
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#define WM1S_LP_ILK 0x45120
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#define WM2S_LP_IVB 0x45124
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#define WM3S_LP_IVB 0x45128
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#define WM1S_LP_EN (1<<31)
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#define WM1S_LP_EN (1UL<<31)
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/* Memory latency timer register */
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#define MLTR_ILK 0x11222
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@ -2730,7 +2730,7 @@
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/* Display A control */
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#define _DSPACNTR 0x70180
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||||
#define DISPLAY_PLANE_ENABLE (1<<31)
|
||||
#define DISPLAY_PLANE_ENABLE (1UL<<31)
|
||||
#define DISPLAY_PLANE_DISABLE 0
|
||||
#define DISPPLANE_GAMMA_ENABLE (1<<30)
|
||||
#define DISPPLANE_GAMMA_DISABLE 0
|
||||
|
|
@ -2831,7 +2831,7 @@
|
|||
|
||||
/* Sprite A control */
|
||||
#define _DVSACNTR 0x72180
|
||||
#define DVS_ENABLE (1<<31)
|
||||
#define DVS_ENABLE (1UL<<31)
|
||||
#define DVS_GAMMA_ENABLE (1<<30)
|
||||
#define DVS_PIXFORMAT_MASK (3<<25)
|
||||
#define DVS_FORMAT_YUV422 (0<<25)
|
||||
|
|
@ -2859,7 +2859,7 @@
|
|||
#define _DVSATILEOFF 0x721a4
|
||||
#define _DVSASURFLIVE 0x721ac
|
||||
#define _DVSASCALE 0x72204
|
||||
#define DVS_SCALE_ENABLE (1<<31)
|
||||
#define DVS_SCALE_ENABLE (1UL<<31)
|
||||
#define DVS_FILTER_MASK (3<<29)
|
||||
#define DVS_FILTER_MEDIUM (0<<29)
|
||||
#define DVS_FILTER_ENHANCING (1<<29)
|
||||
|
|
@ -2896,7 +2896,7 @@
|
|||
#define DVSSURFLIVE(pipe) _PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE)
|
||||
|
||||
#define _SPRA_CTL 0x70280
|
||||
#define SPRITE_ENABLE (1<<31)
|
||||
#define SPRITE_ENABLE (1UL<<31)
|
||||
#define SPRITE_GAMMA_ENABLE (1<<30)
|
||||
#define SPRITE_PIXFORMAT_MASK (7<<25)
|
||||
#define SPRITE_FORMAT_YUV422 (0<<25)
|
||||
|
|
@ -2931,7 +2931,7 @@
|
|||
#define _SPRA_OFFSET 0x702a4
|
||||
#define _SPRA_SURFLIVE 0x702ac
|
||||
#define _SPRA_SCALE 0x70304
|
||||
#define SPRITE_SCALE_ENABLE (1<<31)
|
||||
#define SPRITE_SCALE_ENABLE (1UL<<31)
|
||||
#define SPRITE_FILTER_MASK (3<<29)
|
||||
#define SPRITE_FILTER_MEDIUM (0<<29)
|
||||
#define SPRITE_FILTER_ENHANCING (1<<29)
|
||||
|
|
@ -2972,7 +2972,7 @@
|
|||
|
||||
/* VBIOS regs */
|
||||
#define VGACNTRL 0x71400
|
||||
# define VGA_DISP_DISABLE (1 << 31)
|
||||
# define VGA_DISP_DISABLE (1UL << 31)
|
||||
# define VGA_2X_MODE (1 << 30)
|
||||
# define VGA_PIPE_B_SELECT (1 << 29)
|
||||
|
||||
|
|
@ -3070,7 +3070,7 @@
|
|||
/* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */
|
||||
#define _PFA_CTL_1 0x68080
|
||||
#define _PFB_CTL_1 0x68880
|
||||
#define PF_ENABLE (1<<31)
|
||||
#define PF_ENABLE (1UL<<31)
|
||||
#define PF_PIPE_SEL_MASK_IVB (3<<29)
|
||||
#define PF_PIPE_SEL_IVB(pipe) ((pipe)<<29)
|
||||
#define PF_FILTER_MASK (3<<23)
|
||||
|
|
@ -3099,7 +3099,7 @@
|
|||
#define LGC_PALETTE(pipe) _PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B)
|
||||
|
||||
/* interrupts */
|
||||
#define DE_MASTER_IRQ_CONTROL (1 << 31)
|
||||
#define DE_MASTER_IRQ_CONTROL (1UL << 31)
|
||||
#define DE_SPRITEB_FLIP_DONE (1 << 29)
|
||||
#define DE_SPRITEA_FLIP_DONE (1 << 28)
|
||||
#define DE_PLANEB_FLIP_DONE (1 << 27)
|
||||
|
|
@ -3142,7 +3142,7 @@
|
|||
#define DE_PIPEA_VBLANK_IVB (1<<0)
|
||||
|
||||
#define VLV_MASTER_IER 0x4400c /* Gunit master IER */
|
||||
#define MASTER_INTERRUPT_ENABLE (1<<31)
|
||||
#define MASTER_INTERRUPT_ENABLE (1UL<<31)
|
||||
|
||||
#define DEISR 0x44000
|
||||
#define DEIMR 0x44004
|
||||
|
|
@ -3175,7 +3175,7 @@
|
|||
#define ILK_DPARB_GATE (1<<22)
|
||||
#define ILK_VSDPFD_FULL (1<<21)
|
||||
#define ILK_DISPLAY_CHICKEN_FUSES 0x42014
|
||||
#define ILK_INTERNAL_GRAPHICS_DISABLE (1<<31)
|
||||
#define ILK_INTERNAL_GRAPHICS_DISABLE (1UL<<31)
|
||||
#define ILK_INTERNAL_DISPLAY_DISABLE (1<<30)
|
||||
#define ILK_DISPLAY_DEBUG_DISABLE (1<<29)
|
||||
#define ILK_HDCP_DISABLE (1<<25)
|
||||
|
|
@ -3258,7 +3258,7 @@
|
|||
#define SDE_TRANS_MASK (0x3f)
|
||||
|
||||
/* south display engine interrupt: CPT/PPT */
|
||||
#define SDE_AUDIO_POWER_D_CPT (1 << 31)
|
||||
#define SDE_AUDIO_POWER_D_CPT (1UL << 31)
|
||||
#define SDE_AUDIO_POWER_C_CPT (1 << 30)
|
||||
#define SDE_AUDIO_POWER_B_CPT (1 << 29)
|
||||
#define SDE_AUDIO_POWER_SHIFT_CPT 29
|
||||
|
|
@ -3541,8 +3541,8 @@
|
|||
#define _PCH_TRANSACONF 0xf0008
|
||||
#define _PCH_TRANSBCONF 0xf1008
|
||||
#define PCH_TRANSCONF(plane) _PIPE(plane, _PCH_TRANSACONF, _PCH_TRANSBCONF)
|
||||
#define TRANS_DISABLE (0<<31)
|
||||
#define TRANS_ENABLE (1<<31)
|
||||
#define TRANS_DISABLE (0UL<<31)
|
||||
#define TRANS_ENABLE (1UL<<31)
|
||||
#define TRANS_STATE_MASK (1<<30)
|
||||
#define TRANS_STATE_DISABLE (0<<30)
|
||||
#define TRANS_STATE_ENABLE (1<<30)
|
||||
|
|
@ -3568,7 +3568,7 @@
|
|||
#define _TRANSA_CHICKEN2 0xf0064
|
||||
#define _TRANSB_CHICKEN2 0xf1064
|
||||
#define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
|
||||
#define TRANS_CHICKEN2_TIMING_OVERRIDE (1<<31)
|
||||
#define TRANS_CHICKEN2_TIMING_OVERRIDE (1UL<<31)
|
||||
|
||||
|
||||
#define SOUTH_CHICKEN1 0xc2000
|
||||
|
|
@ -3596,8 +3596,8 @@
|
|||
#define _FDI_TXA_CTL 0x60100
|
||||
#define _FDI_TXB_CTL 0x61100
|
||||
#define FDI_TX_CTL(pipe) _PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL)
|
||||
#define FDI_TX_DISABLE (0<<31)
|
||||
#define FDI_TX_ENABLE (1<<31)
|
||||
#define FDI_TX_DISABLE (0UL<<31)
|
||||
#define FDI_TX_ENABLE (1UL<<31)
|
||||
#define FDI_LINK_TRAIN_PATTERN_1 (0<<28)
|
||||
#define FDI_LINK_TRAIN_PATTERN_2 (1<<28)
|
||||
#define FDI_LINK_TRAIN_PATTERN_IDLE (2<<28)
|
||||
|
|
@ -3647,7 +3647,7 @@
|
|||
#define _FDI_RXA_CTL 0xf000c
|
||||
#define _FDI_RXB_CTL 0xf100c
|
||||
#define FDI_RX_CTL(pipe) _PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL)
|
||||
#define FDI_RX_ENABLE (1<<31)
|
||||
#define FDI_RX_ENABLE (1UL<<31)
|
||||
/* train, dp width same as FDI_TX */
|
||||
#define FDI_FS_ERRC_ENABLE (1<<27)
|
||||
#define FDI_FE_ERRC_ENABLE (1<<26)
|
||||
|
|
@ -3720,7 +3720,7 @@
|
|||
|
||||
/* or SDVOB */
|
||||
#define HDMIB 0xe1140
|
||||
#define PORT_ENABLE (1 << 31)
|
||||
#define PORT_ENABLE (1UL << 31)
|
||||
#define TRANSCODER(pipe) ((pipe) << 30)
|
||||
#define TRANSCODER_CPT(pipe) ((pipe) << 29)
|
||||
#define TRANSCODER_MASK (1 << 30)
|
||||
|
|
@ -3749,7 +3749,7 @@
|
|||
#define PCH_LVDS 0xe1180
|
||||
#define LVDS_DETECTED (1 << 1)
|
||||
#define LVDS_BORDER_ENABLE (1 << 15)
|
||||
#define LVDS_PORT_ENABLE (1 << 31)
|
||||
#define LVDS_PORT_ENABLE (1UL << 31)
|
||||
#define LVDS_CLOCK_A_POWERUP_ALL (3 << 8)
|
||||
#define LVDS_CLOCK_B_POWERUP_ALL (3 << 4)
|
||||
#define LVDS_CLOCK_BOTH_POWERUP_ALL (3 << 2)
|
||||
|
|
@ -3842,7 +3842,7 @@
|
|||
#define TRANS_DP_CTL_B 0xe1300
|
||||
#define TRANS_DP_CTL_C 0xe2300
|
||||
#define TRANS_DP_CTL(pipe) _PIPE(pipe, TRANS_DP_CTL_A, TRANS_DP_CTL_B)
|
||||
#define TRANS_DP_OUTPUT_ENABLE (1<<31)
|
||||
#define TRANS_DP_OUTPUT_ENABLE (1UL<<31)
|
||||
#define TRANS_DP_PORT_SEL_B (0<<29)
|
||||
#define TRANS_DP_PORT_SEL_C (1<<29)
|
||||
#define TRANS_DP_PORT_SEL_D (2<<29)
|
||||
|
|
@ -3929,7 +3929,7 @@
|
|||
#define GEN7_L3BANK2X_CLOCK_GATE_DISABLE (1<<25)
|
||||
|
||||
#define GEN6_RPNSWREQ 0xA008
|
||||
#define GEN6_TURBO_DISABLE (1<<31)
|
||||
#define GEN6_TURBO_DISABLE (1UL<<31)
|
||||
#define GEN6_FREQUENCY(x) ((x)<<25)
|
||||
#define GEN6_OFFSET(x) ((x)<<19)
|
||||
#define GEN6_AGGRESSIVE_TURBO (0<<15)
|
||||
|
|
@ -3941,7 +3941,7 @@
|
|||
#define GEN6_RC_CTL_RC1e_ENABLE (1<<20)
|
||||
#define GEN6_RC_CTL_RC7_ENABLE (1<<22)
|
||||
#define GEN6_RC_CTL_EI_MODE(x) ((x)<<27)
|
||||
#define GEN6_RC_CTL_HW_ENABLE (1<<31)
|
||||
#define GEN6_RC_CTL_HW_ENABLE (1UL<<31)
|
||||
#define GEN6_RP_DOWN_TIMEOUT 0xA010
|
||||
#define GEN6_RP_INTERRUPT_LIMITS 0xA014
|
||||
#define GEN6_RPSTAT1 0xA01C
|
||||
|
|
@ -4009,7 +4009,7 @@
|
|||
#define GEN6_GT_GFX_RC6pp 0x138110
|
||||
|
||||
#define GEN6_PCODE_MAILBOX 0x138124
|
||||
#define GEN6_PCODE_READY (1<<31)
|
||||
#define GEN6_PCODE_READY (1UL<<31)
|
||||
#define GEN6_READ_OC_PARAMS 0xc
|
||||
#define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8
|
||||
#define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9
|
||||
|
|
@ -4180,7 +4180,7 @@
|
|||
#define HSW_PWR_WELL_ENABLE (1UL<<31)
|
||||
#define HSW_PWR_WELL_STATE (1<<30)
|
||||
#define HSW_PWR_WELL_CTL5 0x45410
|
||||
#define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1<<31)
|
||||
#define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1UL<<31)
|
||||
#define HSW_PWR_WELL_PWR_GATE_OVERRIDE (1<<20)
|
||||
#define HSW_PWR_WELL_FORCE_ON (1<<19)
|
||||
#define HSW_PWR_WELL_CTL6 0x45414
|
||||
|
|
@ -4192,7 +4192,7 @@
|
|||
#define TRANS_DDI_FUNC_CTL_EDP 0x6F400
|
||||
#define TRANS_DDI_FUNC_CTL(tran) _TRANSCODER(tran, TRANS_DDI_FUNC_CTL_A, \
|
||||
TRANS_DDI_FUNC_CTL_B)
|
||||
#define TRANS_DDI_FUNC_ENABLE (1<<31)
|
||||
#define TRANS_DDI_FUNC_ENABLE (1UL<<31)
|
||||
/* Those bits are ignored by pipe EDP since it can only connect to DDI A */
|
||||
#define TRANS_DDI_PORT_MASK (7<<28)
|
||||
#define TRANS_DDI_SELECT_PORT(x) ((x)<<28)
|
||||
|
|
@ -4224,7 +4224,7 @@
|
|||
#define DP_TP_CTL_A 0x64040
|
||||
#define DP_TP_CTL_B 0x64140
|
||||
#define DP_TP_CTL(port) _PORT(port, DP_TP_CTL_A, DP_TP_CTL_B)
|
||||
#define DP_TP_CTL_ENABLE (1<<31)
|
||||
#define DP_TP_CTL_ENABLE (1UL<<31)
|
||||
#define DP_TP_CTL_MODE_SST (0<<27)
|
||||
#define DP_TP_CTL_MODE_MST (1<<27)
|
||||
#define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1<<18)
|
||||
|
|
@ -4248,7 +4248,7 @@
|
|||
#define DDI_BUF_CTL_A 0x64000
|
||||
#define DDI_BUF_CTL_B 0x64100
|
||||
#define DDI_BUF_CTL(port) _PORT(port, DDI_BUF_CTL_A, DDI_BUF_CTL_B)
|
||||
#define DDI_BUF_CTL_ENABLE (1<<31)
|
||||
#define DDI_BUF_CTL_ENABLE (1UL<<31)
|
||||
#define DDI_BUF_EMP_400MV_0DB_HSW (0<<24) /* Sel0 */
|
||||
#define DDI_BUF_EMP_400MV_3_5DB_HSW (1<<24) /* Sel1 */
|
||||
#define DDI_BUF_EMP_400MV_6DB_HSW (2<<24) /* Sel2 */
|
||||
|
|
@ -4313,7 +4313,7 @@
|
|||
|
||||
/* SPLL */
|
||||
#define SPLL_CTL 0x46020
|
||||
#define SPLL_PLL_ENABLE (1<<31)
|
||||
#define SPLL_PLL_ENABLE (1UL<<31)
|
||||
#define SPLL_PLL_SSC (1<<28)
|
||||
#define SPLL_PLL_NON_SSC (2<<28)
|
||||
#define SPLL_PLL_FREQ_810MHz (0<<26)
|
||||
|
|
@ -4322,7 +4322,7 @@
|
|||
/* WRPLL */
|
||||
#define WRPLL_CTL1 0x46040
|
||||
#define WRPLL_CTL2 0x46060
|
||||
#define WRPLL_PLL_ENABLE (1<<31)
|
||||
#define WRPLL_PLL_ENABLE (1UL<<31)
|
||||
#define WRPLL_PLL_SELECT_SSC (0x01<<28)
|
||||
#define WRPLL_PLL_SELECT_NON_SSC (0x02<<28)
|
||||
#define WRPLL_PLL_SELECT_LCPLL_2700 (0x03<<28)
|
||||
|
|
@ -4364,7 +4364,7 @@
|
|||
|
||||
/* LCPLL Control */
|
||||
#define LCPLL_CTL 0x130040
|
||||
#define LCPLL_PLL_DISABLE (1<<31)
|
||||
#define LCPLL_PLL_DISABLE (1UL<<31)
|
||||
#define LCPLL_PLL_LOCK (1<<30)
|
||||
#define LCPLL_CLK_FREQ_MASK (3<<26)
|
||||
#define LCPLL_CLK_FREQ_450 (0<<26)
|
||||
|
|
|
|||
|
|
@ -584,7 +584,7 @@ struct bdb_edp {
|
|||
#define SWF11_DPMS_STANDBY (1<<0)
|
||||
#define SWF11_DPMS_ON 0
|
||||
|
||||
#define SWF14_GFX_PFIT_EN (1<<31)
|
||||
#define SWF14_GFX_PFIT_EN (1UL<<31)
|
||||
#define SWF14_TEXT_PFIT_EN (1<<30)
|
||||
#define SWF14_LID_STATUS_CLOSED (1<<29) /* 0 here means open */
|
||||
#define SWF14_POPUP_EN (1<<28)
|
||||
|
|
|
|||
|
|
@ -168,7 +168,7 @@ typedef struct {
|
|||
#define IGD_BACKLIGHT_BRIGHTNESS 0xff
|
||||
#define IGD_INITIAL_BRIGHTNESS 0x64
|
||||
|
||||
#define IGD_FIELD_VALID (1 << 31)
|
||||
#define IGD_FIELD_VALID (1UL << 31)
|
||||
#define IGD_WORD_FIELD_VALID (1 << 15)
|
||||
#define IGD_PFIT_STRETCH 6
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue