mb/google/brya/var/kinox: Modify DDR4 to non-interleaved

Kinox is designed to 8-layer PCB. In order to reduce the length of
memory singals, the DDR4 is designed from interleaved to
non-interleaved.

BUG=b:210094309
TEST=emerge-brask coreboot

Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I03c6fcccf8b1646cec1a35cc1f9cbb1cfb942c4e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62953
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
This commit is contained in:
Dtrain Hsu 2022-03-21 14:51:18 +08:00 committed by Felix Held
parent 1f54599b98
commit 5d3b1bbce4
2 changed files with 32 additions and 0 deletions

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@ -1,5 +1,6 @@
# SPDX-License-Identifier: GPL-2.0-only # SPDX-License-Identifier: GPL-2.0-only
bootblock-y += gpio.c bootblock-y += gpio.c
romstage-y += gpio.c romstage-y += gpio.c
romstage-y += memory.c
ramstage-y += gpio.c ramstage-y += gpio.c
ramstage-y += ramstage.c ramstage-y += ramstage.c

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@ -0,0 +1,31 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <baseboard/gpio.h>
#include <baseboard/variants.h>
#include <gpio.h>
#include <soc/romstage.h>
static const struct mb_cfg ddr4_mem_config = {
.type = MEM_TYPE_DDR4,
.rcomp = {
/* Baseboard uses only 100ohm Rcomp resistors */
.resistor = 100,
/* Baseboard Rcomp target values */
.targets = {50, 20, 25, 25, 25},
},
.ect = 1, /* Early Command Training */
.UserBd = BOARD_TYPE_MOBILE,
.ddr_config = {
.dq_pins_interleaved = false,
},
};
const struct mb_cfg *variant_memory_params(void)
{
return &ddr4_mem_config;
}