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google/reef: Configure SDIO D1 to enable SCS Power Gating 

SDIO D1 pin needs to be configured as Native mode to
enable SCS Power Gating.

BUG=chrome-os-partner:54251
TEST=Verify SCS Power Gating

Change-Id: Ic33b26443203217678e11d195eb965a7e628ad82
Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com>
Reviewed-on: https://review.coreboot.org/16062
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Jagadish Krishnamoorthy 2016-08-04 10:17:22 -07:00 committed by Martin Roth
parent 09ae1d533e
commit 5d3d69ca95
1 changed files with 2 additions and 1 deletions
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3
src/mainboard/google/reef/gpio.h
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@ -53,7 +53,8 @@ static const struct pad_config gpio_table[] = {
/* SDIO -- unused. */ /* SDIO -- unused. */
PAD_CFG_GPI(GPIO_166, UP_20K, DEEP), /* SDIO_CLK */ PAD_CFG_GPI(GPIO_166, UP_20K, DEEP), /* SDIO_CLK */
PAD_CFG_GPI(GPIO_167, UP_20K, DEEP), /* SDIO_D0 */ PAD_CFG_GPI(GPIO_167, UP_20K, DEEP), /* SDIO_D0 */
PAD_CFG_GPI(GPIO_168, UP_20K, DEEP), /* SDIO_D1 */ /* Configure SDIO to enable power gating */
PAD_CFG_NF(GPIO_168, UP_20K, DEEP, NF1), /* SDIO_D1 */
PAD_CFG_GPI(GPIO_169, UP_20K, DEEP), /* SDIO_D2 */ PAD_CFG_GPI(GPIO_169, UP_20K, DEEP), /* SDIO_D2 */
PAD_CFG_GPI(GPIO_170, UP_20K, DEEP), /* SDIO_D3 */ PAD_CFG_GPI(GPIO_170, UP_20K, DEEP), /* SDIO_D3 */
PAD_CFG_GPI(GPIO_171, UP_20K, DEEP), /* SDIO_CMD */ PAD_CFG_GPI(GPIO_171, UP_20K, DEEP), /* SDIO_CMD */