drop quite a lot of dead code that did nothing but produce warnings and make

the rest of the code unreadable.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5426 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

src/cpu/amd/mtrr/amd_earlymtrr.c

@@ -1,97 +0,0 @@
-#ifndef AMD_EARLYMTRR_C
-#define AMD_EARLYMTRR_C
-#include <cpu/x86/mtrr.h>
-#include <cpu/amd/mtrr.h>
-#include "cpu/x86/mtrr/earlymtrr.c"
-
-/* the fixed and variable MTTRs are power-up with random values,
- * clear them to MTRR_TYPE_UNCACHEABLE for safty.
- */             
-static void do_amd_early_mtrr_init(const unsigned long *mtrr_msrs)
-{               
-        /* Precondition:
-         *   The cache is not enabled in cr0 nor in MTRRdefType_MSR
-         *   entry32.inc ensures the cache is not enabled in cr0
-         */
-        msr_t msr;
-        const unsigned long *msr_addr;
-#if 0
-        /* Enable the access to AMD RdDram and WrDram extension bits */
-        msr = rdmsr(SYSCFG_MSR);
-        msr.lo |= SYSCFG_MSR_MtrrFixDramModEn;
-        wrmsr(SYSCFG_MSR, msr);
-#endif
-
-        /* Inialize all of the relevant msrs to 0 */
-        msr.lo = 0;
-        msr.hi = 0;
-        unsigned long msr_nr;
-        for(msr_addr = mtrr_msrs; (msr_nr = *msr_addr); msr_addr++) {
-                wrmsr(msr_nr, msr);
-        }
-#if 0
-        /* Disable the access to AMD RdDram and WrDram extension bits */
-        msr = rdmsr(SYSCFG_MSR);
-        msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn;
-        wrmsr(SYSCFG_MSR, msr);
-#endif
-
-        /* Enable memory access for 0 - 1MB using top_mem */
-        msr.hi = 0;
-        msr.lo = (((CONFIG_RAMTOP) + TOP_MEM_MASK) & ~TOP_MEM_MASK);
-        wrmsr(TOP_MEM, msr);
-
-#if defined(CONFIG_XIP_ROM_SIZE)
-        /* enable write through caching so we can do execute in place
-         * on the flash rom.
-         */
-        set_var_mtrr(1, REAL_XIP_ROM_BASE, CONFIG_XIP_ROM_SIZE, MTRR_TYPE_WRBACK);
-#endif
-
-        /* Set the default memory type and enable fixed and variable MTRRs 
-         */
-        /* Enable Variable MTRRs */
-        msr.hi = 0x00000000;
-        msr.lo = 0x00000800;
-        wrmsr(MTRRdefType_MSR, msr);
-
-        /* Enable the MTRRs in SYSCFG */
-        msr = rdmsr(SYSCFG_MSR);
-        msr.lo |= SYSCFG_MSR_MtrrVarDramEn;
-        wrmsr(SYSCFG_MSR, msr);
-        
-}
-
-static void amd_early_mtrr_init(void)
-{
-	static const unsigned long mtrr_msrs[] = {
-		/* fixed mtrr */
-		0x250, 0x258, 0x259,
-		0x268, 0x269, 0x26A,
-		0x26B, 0x26C, 0x26D,
-		0x26E, 0x26F,
-		/* var mtrr */
-		0x200, 0x201, 0x202, 0x203,
-		0x204, 0x205, 0x206, 0x207,
-		0x208, 0x209, 0x20A, 0x20B,
-		0x20C, 0x20D, 0x20E, 0x20F,
-		/* var iorr */
-		0xC0010016, 0xC0010017, 0xC0010018, 0xC0010019,
-		/* mem top */
-		0xC001001A, 0xC001001D,
-		/* NULL end of table */
-		0
-	};
-
-	/* wbinvd which is called in disable_cache() causes hangs on Opterons
-	 * if there is no data in the cache.
-	 * At this point we should not have the cache enabled so don't bother
-	 * disabling it.
-	 */
-	/* disable_cache(); */
-	do_amd_early_mtrr_init(mtrr_msrs);
-
-	enable_cache();
-}
-
-#endif /* AMD_EARLYMTRR_C */

src/cpu/x86/mtrr/earlymtrr.c

@@ -2,6 +2,7 @@
 #define EARLYMTRR_C
 #include <cpu/x86/cache.h>
 #include <cpu/x86/mtrr.h>
+#include <cpu/amd/mtrr.h>
 #include <cpu/x86/msr.h>
 
 #if 0

src/lib/debug.c

@@ -33,7 +33,7 @@ static inline void print_pci_devices(void)
 {
 	device_t dev;
 	for (dev = PCI_DEV(0, 0, 0);
-	     dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0, 0, 1)) {
+	     dev <= PCI_DEV(0xff, 0x1f, 0x7); dev += PCI_DEV(0, 0, 1)) {
 		u32 id;
 		id = pci_read_config32(dev, PCI_VENDOR_ID);
 		if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff)

src/mainboard/amd/dbm690t/romstage.c

@@ -54,7 +54,7 @@
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "superio/ite/it8712f/it8712f_early_serial.c"
 
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 
 #include "northbridge/amd/amdk8/setup_resource_map.c"

src/mainboard/amd/mahogany/romstage.c

@@ -54,7 +54,7 @@
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "superio/ite/it8718f/it8718f_early_serial.c"
 
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 
 #include "northbridge/amd/amdk8/setup_resource_map.c"

src/mainboard/amd/mahogany_fam10/romstage.c

@@ -71,14 +71,6 @@ static int smbus_read_byte(u32 device, u32 address);
 #include "southbridge/amd/sb700/sb700_early_setup.c"
 #include "northbridge/amd/amdfam10/debug.c"
 
-static void memreset_setup(void)
-{
-}
-
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-}
-
 static void activate_spd_rom(const struct mem_controller *ctrl)
 {
 }
@@ -245,9 +237,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	/* It's the time to set ctrl in sysinfo now; */
 	printk(BIOS_DEBUG, "fill_mem_ctrl()\n");
 	fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
-	post_code(0x3D);
 
-	memreset_setup();
 	post_code(0x40);
 
 //	die("Die Before MCT init.");

src/mainboard/amd/pistachio/romstage.c

@@ -48,7 +48,7 @@
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "superio/ite/it8712f/it8712f_early_serial.c"
 
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 
 #include "northbridge/amd/amdk8/setup_resource_map.c"
@@ -57,7 +57,7 @@
 #include "southbridge/amd/sb600/sb600_early_setup.c"
 #include "northbridge/amd/amdk8/debug.c" /* After sb600_early_setup.c! */
 
-/* CAN'T BE REMOVED! crt0.S will use it. I don't know WHY!*/
+/* CAN'T BE REMOVED! memory bus reset hook for some broken amd k8 boards. */
 static void memreset(int controllers, const struct mem_controller *ctrl)
 {
 }

src/mainboard/amd/serengeti_cheetah_fam10/romstage.c

@@ -68,7 +68,7 @@ int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf,
 
 #include "northbridge/amd/amdfam10/debug.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#include "cpu/x86/mtrr/earlymtrr.c"
 #include "northbridge/amd/amdfam10/setup_resource_map.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
@@ -81,10 +81,6 @@ static void memreset_setup(void)
 	outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
 }
 
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-}
-
 static void activate_spd_rom(const struct mem_controller *ctrl)
 {
 #define SMBUS_HUB 0x18

src/mainboard/arima/hdama/romstage.c

@@ -23,7 +23,7 @@
 #include "northbridge/amd/amdk8/debug.c"
 #include "superio/nsc/pc87360/pc87360_early_serial.c"
 
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 
 #include "northbridge/amd/amdk8/setup_resource_map.c"

src/mainboard/asrock/939a785gmh/romstage.c

@@ -55,7 +55,7 @@
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "superio/winbond/w83627dhg/w83627dhg_early_serial.c"
 
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 
 #include "northbridge/amd/amdk8/setup_resource_map.c"

src/mainboard/asus/a8n_e/romstage.c

@@ -57,7 +57,7 @@
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
 #include "northbridge/amd/amdk8/debug.c"
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
 #include "northbridge/amd/amdk8/coherent_ht.c"

src/mainboard/asus/a8v-e_se/romstage.c

@@ -58,7 +58,7 @@ unsigned int get_sbdn(unsigned bus);
 #include "superio/winbond/w83627ehg/w83627ehg_early_serial.c"
 #include "southbridge/via/vt8237r/vt8237r_early_smbus.c"
 #include "northbridge/amd/amdk8/debug.c" /* After vt8237r_early_smbus.c! */
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
 

src/mainboard/asus/m2v-mx_se/romstage.c

@@ -63,7 +63,7 @@ unsigned int get_sbdn(unsigned bus);
 #include "northbridge/amd/amdk8/early_ht.c"
 #include "superio/ite/it8712f/it8712f_early_serial.c"
 #include "southbridge/via/vt8237r/vt8237r_early_smbus.c"
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
 

src/mainboard/broadcom/blast/romstage.c

@@ -29,7 +29,7 @@
 #include "northbridge/amd/amdk8/debug.c"
 #include "superio/nsc/pc87417/pc87417_early_serial.c"
 
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 
 #include "northbridge/amd/amdk8/setup_resource_map.c"

src/mainboard/dell/s1850/romstage.c

@@ -41,10 +41,6 @@
 #define RECVENA_CONFIG  0x0808090a
 #define RECVENB_CONFIG  0x0808090a
 
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
-	/* nothing to do */
-}
 static inline int spd_read_byte(unsigned device, unsigned address)
 {
 	return smbus_read_byte(device, address);
@@ -339,7 +335,6 @@ static void main(unsigned long bist)
 	disable_watchdogs();
 //	dump_ipmi_registers();
 	mainboard_set_e7520_leds();	
-//	memreset_setup();
 
 	sdram_initialize(ARRAY_SIZE(mch), mch);
 #if 0

src/mainboard/digitallogic/msm586seg/romstage.c

@@ -44,19 +44,6 @@ struct mem_controller {
 	int i;
 };
 
-static void memreset_setup(void)
-{
-}
-
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-}
-
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
-        /* nothing to do */
-}
- 
 static inline int spd_read_byte(unsigned device, unsigned address)
 {
 //	return smbus_read_byte(device, address);

src/mainboard/gigabyte/ga_2761gxdk/romstage.c

@@ -78,7 +78,7 @@
 
 #include "northbridge/amd/amdk8/debug.c"
 
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#include "cpu/x86/mtrr/earlymtrr.c"
 
 #include "northbridge/amd/amdk8/setup_resource_map.c"
 

src/mainboard/gigabyte/m57sli/romstage.c

@@ -75,7 +75,7 @@
 
 #include "northbridge/amd/amdk8/debug.c"
 
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#include "cpu/x86/mtrr/earlymtrr.c"
 
 #include "northbridge/amd/amdk8/setup_resource_map.c"
 

src/mainboard/hp/dl145_g3/romstage.c

@@ -79,7 +79,7 @@
 
 #include "northbridge/amd/amdk8/debug.c"
 
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#include "cpu/x86/mtrr/earlymtrr.c"
 
 #include "northbridge/amd/amdk8/setup_resource_map.c"
 
@@ -88,10 +88,6 @@
 
 #include "southbridge/broadcom/bcm5785/bcm5785_early_setup.c"
 
-static void memreset_setup(void)
-{
-}
-
 static void memreset(int controllers, const struct mem_controller *ctrl)
 {
 }
@@ -188,12 +184,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 		// first node
 		 DIMM0, DIMM2, 0, 0,
 		 DIMM1, DIMM3, 0, 0,
-#if CONFIG_MAX_PHYSICAL_CPUS > 1
+
 		// second node
 		DIMM4, DIMM6, 0, 0,
 		DIMM5, DIMM7, 0, 0,
-#endif
-
 	};
 
 	struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
@@ -284,7 +278,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 	enable_smbus();
 
-	memreset_setup();
 	//do we need apci timer, tsc...., only debug need it for better output
 	/* all ap stopped? */
 	// init_timer(); // Need to use TMICT to synconize FID/VID

src/mainboard/ibm/e325/romstage.c

@@ -25,7 +25,7 @@
 #include "northbridge/amd/amdk8/debug.c"
 #include "superio/nsc/pc87366/pc87366_early_serial.c"
 
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 
 #include "northbridge/amd/amdk8/setup_resource_map.c"

src/mainboard/ibm/e326/romstage.c

@@ -25,7 +25,7 @@
 #include "northbridge/amd/amdk8/debug.c"
 #include "superio/nsc/pc87366/pc87366_early_serial.c"
 
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 
 #include "northbridge/amd/amdk8/setup_resource_map.c"

src/mainboard/intel/eagleheights/romstage.c

@@ -102,10 +102,6 @@
 #define RCBA_FD    0x3418 /* 32 bit */
 #define RCBA_PRC   0x341C /* 32 bit */
 
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
-	/* nothing to do */
-}
 static inline int spd_read_byte(u16 device, u8 address)
 {
 	return smbus_read_byte(device, address);
@@ -119,8 +115,8 @@ static inline int spd_read_byte(u16 device, u8 address)
 #include "northbridge/intel/i3100/reset_test.c"
 #include "debug.c"
 
-void early_config(void) {
+static void early_config(void)
-	device_t dev;
+{
 	u32 gcs, rpc, fd;
 
 	/* Enable RCBA */

src/mainboard/intel/jarrell/romstage.c

@@ -38,10 +38,6 @@
 #define RECVENB_CONFIG  0x000a090a
 #define DIMM_MAP_LOGICAL 0x0124
 
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
-	/* nothing to do */
-}
 static inline int spd_read_byte(unsigned device, unsigned address)
 {
 	return smbus_read_byte(device, address);

src/mainboard/intel/mtarvon/romstage.c

@@ -46,10 +46,6 @@
 #define DEVPRES_CONFIG  (DEVPRES_D1F0 | DEVPRES_D2F0)
 #define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
 
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
-	/* nothing to do */
-}
 static inline int spd_read_byte(u16 device, u8 address)
 {
 	return smbus_read_byte(device, address);

src/mainboard/intel/truxton/romstage.c

@@ -46,10 +46,6 @@
 
 #define DEVPRES_CONFIG  (DEVPRES_D1F0 | DEVPRES_D2F0 | DEVPRES_D3F0 | DEVPRES_D4F0)
 
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
-	/* nothing to do */
-}
 static inline int spd_read_byte(u16 device, u8 address)
 {
 	return smbus_read_byte(device, address);

src/mainboard/intel/xe7501devkit/reset.c

@@ -1,3 +1,5 @@
+#include <reset.h>
+
 void i82801cx_hard_reset(void);
 
 void hard_reset(void)

src/mainboard/intel/xe7501devkit/romstage.c

@@ -27,11 +27,6 @@ static void hard_reset(void)
         outb(0x0e, 0x0cf9);
 }
 
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
-        /* nothing to do */
-}
- 
 static inline int spd_read_byte(unsigned device, unsigned address)
 {
 	return smbus_read_byte(device, address);
@@ -56,7 +51,6 @@ static void main(unsigned long bist)
 	if (bist == 0) 
 	{
 		// Skip this if there was a built in self test failure
-
 		early_mtrr_init();
 		enable_lapic();
 	}
@@ -79,8 +73,6 @@ static void main(unsigned long bist)
 		enable_smbus();
 		// dump_spd_registers(&memctrl[0]);
 		// dump_smbus_registers();
-
-//		memreset_setup();		No-op for this chipset
 		sdram_initialize(ARRAY_SIZE(memctrl), memctrl);
 	}
 	

src/mainboard/iwill/dk8_htx/romstage.c

@@ -44,7 +44,7 @@
 #include "lib/delay.c"
 
 #include "northbridge/amd/amdk8/debug.c"
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#include "cpu/x86/mtrr/earlymtrr.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 
 #include "northbridge/amd/amdk8/setup_resource_map.c"
@@ -129,17 +129,16 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 			// first node
                         DIMM0, DIMM2, 0, 0,
                         DIMM1, DIMM3, 0, 0,
-#if CONFIG_MAX_PHYSICAL_CPUS > 1
+
 			// second node
                         DIMM4, DIMM6, 0, 0,
                         DIMM5, DIMM7, 0, 0,
-#endif
-
 	};
 
-	struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+	struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
+		+ CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 
-        int needs_reset; int i;
+        int needs_reset;
         unsigned bsp_apicid = 0;
 
         if (!cpu_init_detectedx && boot_cpu()) {

src/mainboard/iwill/dk8s2/romstage.c

@@ -44,7 +44,7 @@
 #include "lib/delay.c"
 
 #include "northbridge/amd/amdk8/debug.c"
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#include "cpu/x86/mtrr/earlymtrr.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 
 #include "northbridge/amd/amdk8/setup_resource_map.c"
@@ -129,17 +129,16 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 			// first node
                         DIMM0, DIMM2, 0, 0,
                         DIMM1, DIMM3, 0, 0,
-#if CONFIG_MAX_PHYSICAL_CPUS > 1
+
 			// second node
                         DIMM4, DIMM6, 0, 0,
                         DIMM5, DIMM7, 0, 0,
-#endif
-
 	};
 
-	struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+	struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
+		+ CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 
-        int needs_reset; int i;
+        int needs_reset;
         unsigned bsp_apicid = 0;
 
         if (!cpu_init_detectedx && boot_cpu()) {

src/mainboard/iwill/dk8x/romstage.c

@@ -44,7 +44,7 @@
 #include "lib/delay.c"
 
 #include "northbridge/amd/amdk8/debug.c"
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#include "cpu/x86/mtrr/earlymtrr.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 
 #include "northbridge/amd/amdk8/setup_resource_map.c"
@@ -129,17 +129,16 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 			// first node
                         DIMM0, DIMM2, 0, 0,
                         DIMM1, DIMM3, 0, 0,
-#if CONFIG_MAX_PHYSICAL_CPUS > 1
+
 			// second node
                         DIMM4, DIMM6, 0, 0,
                         DIMM5, DIMM7, 0, 0,
-#endif
-
 	};
 
-	struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+	struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
+		+ CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 
-        int needs_reset; int i;
+        int needs_reset;
         unsigned bsp_apicid = 0;
 
         if (!cpu_init_detectedx && boot_cpu()) {

src/mainboard/kontron/kt690/romstage.c

@@ -56,7 +56,7 @@
 #include "northbridge/amd/amdk8/debug.c"
 #include "superio/winbond/w83627dhg/w83627dhg_early_serial.c"
 
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 
 #include "northbridge/amd/amdk8/setup_resource_map.c"

src/mainboard/msi/ms7135/irq_tables.c

@@ -62,8 +62,6 @@ static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus,
 	pirq_info->rfu = rfu;
 }
 
-void pci_assign_irqs(unsigned, unsigned, const unsigned char *);
-
 /**
  * Create the IRQ routing table.
  * Values are derived from getpir generated code.

src/mainboard/msi/ms7135/romstage.c

@@ -59,7 +59,7 @@
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
 #include "northbridge/amd/amdk8/debug.c"
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
 #include "northbridge/amd/amdk8/coherent_ht.c"
@@ -98,7 +98,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 
 static void sio_setup(void)
 {
-	unsigned value;
 	uint32_t dword;
 	uint8_t byte;
 

src/mainboard/msi/ms7260/romstage.c

@@ -75,7 +75,7 @@
 
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/debug.c"
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#include "cpu/x86/mtrr/earlymtrr.c"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
 
 /* Yes, on the MSI K9N Neo (MS-7260) the Super I/O is at 0x4e! */

src/mainboard/msi/ms9185/romstage.c

@@ -63,7 +63,7 @@
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/debug.c"
 #include "superio/nsc/pc87417/pc87417_early_serial.c"
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 
 #include "northbridge/amd/amdk8/setup_resource_map.c"

src/mainboard/msi/ms9282/romstage.c

@@ -58,7 +58,7 @@
 #include "northbridge/amd/amdk8/debug.c"
 #include "superio/winbond/w83627ehg/w83627ehg_early_serial.c"
 
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 
 #include "northbridge/amd/amdk8/setup_resource_map.c"

src/mainboard/msi/ms9652_fam10/romstage.c

@@ -67,7 +67,7 @@
 
 #include "northbridge/amd/amdfam10/debug.c"
 
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#include "cpu/x86/mtrr/earlymtrr.c"
 
 #include "northbridge/amd/amdfam10/setup_resource_map.c"
 
@@ -76,14 +76,6 @@
 
 #include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
 
-static void memreset_setup(void)
-{
-}
-
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-}
-
 static inline void activate_spd_rom(const struct mem_controller *ctrl)
 {
 	/* nothing to do */
@@ -292,9 +284,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	printk(BIOS_DEBUG, "enable_smbus()\n");
 	enable_smbus();
-	post_code(0x3E);
 
-	memreset_setup();
 	post_code(0x40);
 
 	printk(BIOS_DEBUG, "raminit_amdmct()\n");

src/mainboard/newisys/khepri/romstage.c

@@ -31,7 +31,7 @@
 #include "northbridge/amd/amdk8/debug.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 
 #include "northbridge/amd/amdk8/setup_resource_map.c"

src/mainboard/nvidia/l1_2pvv/romstage.c

@@ -75,7 +75,7 @@
 
 #include "northbridge/amd/amdk8/debug.c"
 
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#include "cpu/x86/mtrr/earlymtrr.c"
 
 #include "northbridge/amd/amdk8/setup_resource_map.c"
 

src/mainboard/sunw/ultra40/romstage.c

@@ -32,7 +32,7 @@
 #include "northbridge/amd/amdk8/debug.c"
 #include "superio/smsc/lpc47b397/lpc47b397_early_serial.c"
 
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 
 #include "superio/smsc/lpc47b397/lpc47b397_early_gpio.c"

src/mainboard/supermicro/h8dme/romstage.c

@@ -69,7 +69,7 @@
 
 #include "northbridge/amd/amdk8/debug.c"
 
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#include "cpu/x86/mtrr/earlymtrr.c"
 
 #include "northbridge/amd/amdk8/setup_resource_map.c"
 

src/mainboard/supermicro/h8dmr/romstage.c

@@ -72,7 +72,7 @@
 
 #include "northbridge/amd/amdk8/debug.c"
 
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#include "cpu/x86/mtrr/earlymtrr.c"
 
 #include "northbridge/amd/amdk8/setup_resource_map.c"
 

src/mainboard/supermicro/h8dmr_fam10/romstage.c

@@ -65,7 +65,7 @@
 
 #include "northbridge/amd/amdfam10/debug.c"
 
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#include "cpu/x86/mtrr/earlymtrr.c"
 
 #include "northbridge/amd/amdfam10/setup_resource_map.c"
 
@@ -73,14 +73,6 @@
 
 #include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
 
-static void memreset_setup(void)
-{
-}
-
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-}
-
 static inline void activate_spd_rom(const struct mem_controller *ctrl)
 {
 	/* nothing to do */
@@ -281,10 +273,6 @@ post_code(0x3D);
 //printk(BIOS_DEBUG, "enable_smbus()\n");
 //        enable_smbus(); /* enable in sio_setup */
 
-post_code(0x3E);
-
-        memreset_setup();
-
 post_code(0x40);
 
  printk(BIOS_DEBUG, "raminit_amdmct()\n");

src/mainboard/supermicro/h8qme_fam10/romstage.c

@@ -66,7 +66,7 @@
 
 #include "northbridge/amd/amdfam10/debug.c"
 
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#include "cpu/x86/mtrr/earlymtrr.c"
 
 #include "northbridge/amd/amdfam10/setup_resource_map.c"
 
@@ -74,14 +74,6 @@
 
 #include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
 
-static void memreset_setup(void)
-{
-}
-
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-}
-
 static inline void activate_spd_rom(const struct mem_controller *ctrl)
 {
 #define SMBUS_SWITCH1 0x70
@@ -326,10 +318,6 @@ post_code(0x3D);
 //printk(BIOS_DEBUG, "enable_smbus()\n");
 //        enable_smbus(); /* enable in sio_setup */
 
-post_code(0x3E);
-
-        memreset_setup();
-
 post_code(0x40);
 
  printk(BIOS_DEBUG, "raminit_amdmct()\n");

src/mainboard/supermicro/x6dai_g/romstage.c

@@ -40,10 +40,6 @@
 #define RECVENA_CONFIG  0x0808090a
 #define RECVENB_CONFIG  0x0808090a
 
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
-	/* nothing to do */
-}
 static inline int spd_read_byte(unsigned device, unsigned address)
 {
 	return smbus_read_byte(device, address);

src/mainboard/supermicro/x6dhe_g/romstage.c

@@ -41,10 +41,6 @@
 #define RECVENA_CONFIG  0x0808090a
 #define RECVENB_CONFIG  0x0808090a
 
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
-	/* nothing to do */
-}
 static inline int spd_read_byte(unsigned device, unsigned address)
 {
 	return smbus_read_byte(device, address);
@@ -121,7 +117,6 @@ static void main(unsigned long bist)
 	disable_watchdogs();
 //	dump_ipmi_registers();
 //	mainboard_set_e7520_leds();	
-//	memreset_setup();
 	sdram_initialize(ARRAY_SIZE(mch), mch);
 #if 0
 	dump_pci_devices();

src/mainboard/supermicro/x6dhe_g2/romstage.c

@@ -41,10 +41,6 @@
 #define RECVENA_CONFIG  0x0708090a
 #define RECVENB_CONFIG  0x0708090a
 
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
-	/* nothing to do */
-}
 static inline int spd_read_byte(unsigned device, unsigned address)
 {
 	return smbus_read_byte(device, address);
@@ -122,7 +118,6 @@ static void main(unsigned long bist)
 	disable_watchdogs();
 //	dump_ipmi_registers();
 //	mainboard_set_e7520_leds();	
-//	memreset_setup();
 	sdram_initialize(ARRAY_SIZE(mch), mch);
 #if 0
 	dump_pci_devices();

src/mainboard/supermicro/x6dhr_ig/romstage.c

@@ -42,10 +42,6 @@
 #define RECVENA_CONFIG  0x0808090a
 #define RECVENB_CONFIG  0x0808090a
 
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
-	/* nothing to do */
-}
 static inline int spd_read_byte(unsigned device, unsigned address)
 {
 	return smbus_read_byte(device, address);
@@ -122,7 +118,6 @@ static void main(unsigned long bist)
 	disable_watchdogs();
 //	dump_ipmi_registers();
 	mainboard_set_e7520_leds();	
-//	memreset_setup();
 	sdram_initialize(ARRAY_SIZE(mch), mch);
 #if 1
 	dump_pci_devices();

src/mainboard/supermicro/x6dhr_ig2/romstage.c

@@ -42,10 +42,6 @@
 #define RECVENA_CONFIG  0x0808090a
 #define RECVENB_CONFIG  0x0808090a
 
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
-	/* nothing to do */
-}
 static inline int spd_read_byte(unsigned device, unsigned address)
 {
 	return smbus_read_byte(device, address);
@@ -122,7 +118,6 @@ static void main(unsigned long bist)
 	disable_watchdogs();
 //	dump_ipmi_registers();
 	mainboard_set_e7520_leds();	
-//	memreset_setup();
 	sdram_initialize(ARRAY_SIZE(mch), mch);
 #if 0
 	dump_pci_devices();

src/mainboard/technexion/tim5690/romstage.c

@@ -55,7 +55,7 @@
 #include "northbridge/amd/amdk8/debug.c"
 #include "superio/ite/it8712f/it8712f_early_serial.c"
 
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 
 #include "northbridge/amd/amdk8/setup_resource_map.c"

src/mainboard/technexion/tim8690/romstage.c

@@ -55,7 +55,7 @@
 #include "northbridge/amd/amdk8/debug.c"
 #include "superio/ite/it8712f/it8712f_early_serial.c"
 
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 
 #include "northbridge/amd/amdk8/setup_resource_map.c"

src/mainboard/tyan/s2735/romstage.c

@@ -41,19 +41,6 @@ static void soft_reset(void)
 #endif
 }
 
-static void memreset_setup(void)
-{
-}
-
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-}
-
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
-	/* nothing to do */
-}
-
 static inline int spd_read_byte(unsigned device, unsigned address)
 {
 	return smbus_read_byte(device, address);
@@ -76,11 +63,8 @@ void main(unsigned long bist)
 	
 	unsigned cpu_reset = 0;
 
-       if (bist == 0) 
+	if (bist == 0) {
-	{
-//		early_mtrr_init();
 		enable_lapic();
-
 	}
 
 //	post_code(0x32);
@@ -106,7 +90,6 @@ void main(unsigned long bist)
 	dump_smbus_registers();
 #endif
 
-	memreset_setup();
 	sdram_initialize(1, memctrl);
 
 #if 0

src/mainboard/tyan/s2850/romstage.c

@@ -25,7 +25,7 @@
 #include "northbridge/amd/amdk8/debug.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 
 #include "northbridge/amd/amdk8/setup_resource_map.c"

src/mainboard/tyan/s2875/romstage.c

@@ -25,7 +25,7 @@
 #include "northbridge/amd/amdk8/debug.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 
 #include "northbridge/amd/amdk8/setup_resource_map.c"

src/mainboard/tyan/s2880/romstage.c

@@ -25,7 +25,7 @@
 #include "northbridge/amd/amdk8/debug.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 
 #include "northbridge/amd/amdk8/setup_resource_map.c"

src/mainboard/tyan/s2881/romstage.c

@@ -30,7 +30,7 @@
 #include "northbridge/amd/amdk8/debug.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 
 #include "northbridge/amd/amdk8/setup_resource_map.c"

src/mainboard/tyan/s2882/romstage.c

@@ -25,7 +25,7 @@
 #include "northbridge/amd/amdk8/debug.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 
 #include "northbridge/amd/amdk8/setup_resource_map.c"

src/mainboard/tyan/s2885/romstage.c

@@ -25,7 +25,7 @@
 #include "northbridge/amd/amdk8/debug.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 
 #include "northbridge/amd/amdk8/setup_resource_map.c"

src/mainboard/tyan/s2891/romstage.c

@@ -30,7 +30,7 @@
 #include "northbridge/amd/amdk8/debug.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 
 #include "northbridge/amd/amdk8/setup_resource_map.c"

src/mainboard/tyan/s2892/romstage.c

@@ -31,7 +31,7 @@
 #include "northbridge/amd/amdk8/debug.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 
 #include "northbridge/amd/amdk8/setup_resource_map.c"

src/mainboard/tyan/s2912/romstage.c

@@ -75,7 +75,7 @@
 
 #include "northbridge/amd/amdk8/debug.c"
 
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#include "cpu/x86/mtrr/earlymtrr.c"
 
 #include "northbridge/amd/amdk8/setup_resource_map.c"
 

src/mainboard/tyan/s2912_fam10/romstage.c

@@ -68,7 +68,7 @@
 
 #include "northbridge/amd/amdfam10/debug.c"
 
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#include "cpu/x86/mtrr/earlymtrr.c"
 
 #include "northbridge/amd/amdfam10/setup_resource_map.c"
 
@@ -76,14 +76,6 @@
 
 #include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
 
-static void memreset_setup(void)
-{
-}
-
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-}
-
 static inline void activate_spd_rom(const struct mem_controller *ctrl)
 {
 	/* nothing to do */
@@ -287,9 +279,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	printk(BIOS_DEBUG, "enable_smbus()\n");
 	enable_smbus();
-	post_code(0x3E);
 
-	memreset_setup();
 	post_code(0x40);
 
 	printk(BIOS_DEBUG, "raminit_amdmct()\n");

src/mainboard/tyan/s4880/romstage.c

@@ -25,7 +25,7 @@
 #include "northbridge/amd/amdk8/debug.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 
 #include "northbridge/amd/amdk8/setup_resource_map.c"

src/mainboard/tyan/s4882/romstage.c

@@ -24,7 +24,7 @@
 #include "northbridge/amd/amdk8/debug.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 
 #include "northbridge/amd/amdk8/setup_resource_map.c"

src/mainboard/via/epia-cn/romstage.c

@@ -38,10 +38,6 @@
 #include "southbridge/via/vt8237r/vt8237r_early_smbus.c"
 #include "southbridge/via/vt8235/vt8235_early_serial.c"
 
-static void memreset_setup(void)
-{
-}
-
 static inline int spd_read_byte(unsigned device, unsigned address)
 {
 	return smbus_read_byte(device, address);

src/mainboard/via/epia-m/romstage.c

@@ -1,9 +1,6 @@
 #include <stdint.h>
 #include <device/pci_def.h>
 #include <device/pci_ids.h>
-#if 0
-#include <cpu/x86/lapic.h>
-#endif
 #include <arch/io.h>
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
@@ -22,10 +19,6 @@
 #include "southbridge/via/vt8235/vt8235_early_smbus.c"
 #include "southbridge/via/vt8235/vt8235_early_serial.c"
 
-static void memreset_setup(void)
-{
-}
-
 static inline int spd_read_byte(unsigned device, unsigned address)
 {
 	return smbus_read_byte(device, address);

src/mainboard/via/epia-n/romstage.c

@@ -54,10 +54,6 @@ static const struct mem_controller ctrl = {
 	.channel0 = { 0x50 },
 };
 
-static void memreset_setup(void)
-{
-}
-
 static inline int spd_read_byte(unsigned device, unsigned address)
 {
 	return smbus_read_byte(device, address);

src/northbridge/intel/e7501/raminit.c

@@ -1919,14 +1919,11 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl)
 
 	RAM_DEBUG_MESSAGE("Reading SPD data...\n");
 
-   //activate_spd_rom(ctrl);	Not necessary for this chipset
-
 	dimm_mask = spd_get_supported_dimms(ctrl);
 
 	if (dimm_mask == 0) {
 		print_debug("No usable memory for this controller\n");
 	} else {
-
 		enable_e7501_clocks(dimm_mask);
 
 		RAM_DEBUG_MESSAGE("setting based on SPD data...\n");

src/northbridge/intel/i3100/raminit.c

@@ -88,7 +88,7 @@ static struct dimm_size spd_get_dimm_size(u16 device)
 {
 	/* Calculate the log base 2 size of a DIMM in bits */
 	struct dimm_size sz;
-	int value, low, ddr2;
+	int value, low;
 	sz.side1 = 0;
 	sz.side2 = 0;
 
@@ -594,8 +594,6 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl,
 
 	goto out;
 
- val_err:
-	die("Bad SPD value\n");
 	/* If an hw_error occurs report that I have no memory */
  hw_err:
 	drc = 0;
@@ -715,7 +713,6 @@ static void set_receive_enable(const struct mem_controller *ctrl)
 	u32 dimm;
 	u32 edge;
 	int32_t data32;
-	u32 data32_dram;
 	u32 dcal_data32_0;
 	u32 dcal_data32_1;
 	u32 dcal_data32_2;
@@ -948,10 +945,6 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 	u32 data32;
 	u32 mode_reg;
 	u32 *iptr;
-	volatile u32 *iptrv;
-	msr_t msr;
-	u32 scratch;
-	u8 byte;
 	u16 data16;
 	static const struct {
 		u32 clkgr[4];

src/northbridge/via/vt8623/northbridge.c

@@ -60,7 +60,7 @@ static void northbridge_init(device_t dev)
 	}
 }
 
-static void nullfunc(void)
+static void nullfunc(device_t dev)
 {
 	/* Nothing to do */
 }