soc/intel/skylake: Add Kabylake device Ids

Adding kabylake device ids for chip inits.
Skylake and Kabylak do not differ much, the intention
is to support both SoCs in the same code base.

Change-Id: I9ff4c6ca08fe681798001ce81cca2c085ce32325
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/16049
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>

src/soc/intel/skylake/cpu.c

@@ -382,6 +382,8 @@ static struct device_operations cpu_dev_ops = {
 static struct cpu_device_id cpu_table[] = {
 	{ X86_VENDOR_INTEL, CPUID_SKYLAKE_C0 },
 	{ X86_VENDOR_INTEL, CPUID_SKYLAKE_D0 },
+	{ X86_VENDOR_INTEL, CPUID_KABYLAKE_G0 },
+	{ X86_VENDOR_INTEL, CPUID_KABYLAKE_H0 },
 	{ 0, 0 },
 };
 

src/soc/intel/skylake/include/soc/cpu.h

@@ -26,6 +26,8 @@
 /* Supported CPUIDs */
 #define CPUID_SKYLAKE_C0	0x406e2
 #define CPUID_SKYLAKE_D0	0x406e3
+#define CPUID_KABYLAKE_G0	0x406e8
+#define CPUID_KABYLAKE_H0	0x806e9
 
 /* CPU bus clock is fixed at 100MHz */
 #define CPU_BCLK		100

src/soc/intel/skylake/include/soc/pch.h

@@ -26,6 +26,8 @@
 #define PCH_SPT_LP_U_BASE		0x9d43
 #define PCH_SPT_LP_U_PREMIUM		0x9d48
 #define PCH_SPT_LP_Y_PREMIUM		0x9d46
+#define PCH_KBL_LP_U_PREMIUM		0x9d58
+#define PCH_KBL_LP_Y_PREMIUM		0x9d56
 
 u8 pch_revision(void);
 u16 pch_type(void);

src/soc/intel/skylake/include/soc/systemagent.h

@@ -25,10 +25,15 @@
 #define IGD_SKYLAKE_GT1_SULTM	0x1906
 #define IGD_SKYLAKE_GT2_SULXM	0x191E
 #define IGD_SKYLAKE_GT2_SULTM	0x1916
+#define IGD_KABYLAKE_GT1_SULTM	0x5906
+#define IGD_KABYLAKE_GT2_SULXM	0x591E
+#define IGD_KABYLAKE_GT2_SULTM	0x5916
 
 #define MCH_SKYLAKE_ID_U	0x1904
 #define MCH_SKYLAKE_ID_Y	0x190c
 #define MCH_SKYLAKE_ID_ULX	0x1924
+#define MCH_KABYLAKE_ID_U	0x5904
+#define MCH_KABYLAKE_ID_Y	0x590c
 
 /* Device 0:0.0 PCI configuration space */
 

src/soc/intel/skylake/lpc.c

@@ -317,6 +317,8 @@ static const unsigned short pci_device_ids[] = {
 	PCH_SPT_LP_U_BASE,
 	PCH_SPT_LP_U_PREMIUM,
 	PCH_SPT_LP_Y_PREMIUM,
+	PCH_KBL_LP_U_PREMIUM,
+	PCH_KBL_LP_Y_PREMIUM,
 	0
 };
 

src/soc/intel/skylake/romstage/report_platform.c

@@ -32,6 +32,8 @@ static struct {
 } cpu_table[] = {
 	{ CPUID_SKYLAKE_C0,	"Skylake C0" },
 	{ CPUID_SKYLAKE_D0,	"Skylake D0" },
+	{ CPUID_KABYLAKE_G0,	"Kabylake G0" },
+	{ CPUID_KABYLAKE_H0,	"Kabylake H0" },
 };
 
 static struct {
@@ -41,6 +43,8 @@ static struct {
 	{ MCH_SKYLAKE_ID_U,	"Skylake-U" },
 	{ MCH_SKYLAKE_ID_Y,	"Skylake-Y" },
 	{ MCH_SKYLAKE_ID_ULX,	"Skylake-ULX" },
+	{ MCH_KABYLAKE_ID_U,	"Kabylake-U" },
+	{ MCH_KABYLAKE_ID_Y,	"Kabylake-Y" },
 };
 
 static struct {
@@ -51,6 +55,8 @@ static struct {
 	{ PCH_SPT_LP_U_BASE,	"Skylake-U Base" },
 	{ PCH_SPT_LP_U_PREMIUM,	"Skylake-U Premium" },
 	{ PCH_SPT_LP_Y_PREMIUM,	"Skylake-Y Premium" },
+	{ PCH_KBL_LP_U_PREMIUM, "Kabylake-U Premium" },
+	{ PCH_KBL_LP_Y_PREMIUM, "Kabylake-Y Premium" },
 };
 
 static struct {

src/soc/intel/skylake/systemagent.c

@@ -414,6 +414,8 @@ static const unsigned short systemagent_ids[] = {
 	MCH_SKYLAKE_ID_U,
 	MCH_SKYLAKE_ID_Y,
 	MCH_SKYLAKE_ID_ULX,
+	MCH_KABYLAKE_ID_U,
+	MCH_KABYLAKE_ID_Y,
 	0
 };