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Commit for IDE NAND FLASH 

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2306 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Ronald G. Minnich 2006-05-16 02:51:16 +00:00
parent 98e904ea7c
commit 5d573c28e7
3 changed files with 55 additions and 1 deletions
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1
src/mainboard/olpc/rev_a/Config.lb
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@ -134,6 +134,7 @@ chip northbridge/amd/gx2
device pci 1.1 on end device pci 1.1 on end
chip southbridge/amd/cs5536 chip southbridge/amd/cs5536
register "enable_gpio0_inta" = "1" register "enable_gpio0_inta" = "1"
register "enable_ide_nand_flash" = "1"
device pci d.0 on end # Realtek 8139 LAN device pci d.0 on end # Realtek 8139 LAN
device pci f.0 on end # ISA Bridge device pci f.0 on end # ISA Bridge
device pci f.2 on end # IDE Controller device pci f.2 on end # IDE Controller

1
src/southbridge/amd/cs5536/chip.h
View File

@ -8,6 +8,7 @@ struct southbridge_amd_cs5536_config {
int lpc_serirq_enable; /* how to enable, e.g. 0x80 */ int lpc_serirq_enable; /* how to enable, e.g. 0x80 */
int lpc_irq; /* what to enable, e.g. 0x18 */ int lpc_irq; /* what to enable, e.g. 0x18 */
int enable_gpio0_inta; /* almost always will be true */ int enable_gpio0_inta; /* almost always will be true */
int enable_ide_nand_flash; /* if you are using nand flash instead of IDE drive */
}; };
#endif /* _SOUTHBRIDGE_AMD_CS5536 */ #endif /* _SOUTHBRIDGE_AMD_CS5536 */

54
src/southbridge/amd/cs5536/cs5536.c
View File

@ -15,6 +15,55 @@ static void southbridge_init(struct device *dev)
setup_i8259(); setup_i8259();
} }
#define PIN_OPT_IDE (1ULL<<0) /* 0 for flash, 1 for IDE */
/* Intended value for LBAR_FLSH0: 4KiB, enabled, MMIO, NAND, @0x20000000 */
msr_t flsh0 = { .hi=0xFFFFF007, .lo=0x20000000};
static void
enable_ide_nand_flash(){
msr_t msr;
printk_err("cs5536: %s\n", __FUNCTION__);
msr = rdmsr(MDD_LBAR_FLSH0);
if ( ((msr.hi) & 7) != 7) {
printk_err("MDD_LBAR_FLSH0 was 0x%08x%08x\n", msr.hi,msr.lo);
wrmsr(MDD_LBAR_FLSH0, flsh0);
}
msr = rdmsr(MDD_LBAR_FLSH0);
printk_err("MDD_LBAR_FLSH0 is 0x%08x%08x\n", msr.hi,msr.lo);
msr = rdmsr(MDD_PIN_OPT);
if (msr.lo & PIN_OPT_IDE) {
printk_err("MDD_PIN_OPT was 0x%08x%08x\n", msr.hi,msr.lo);
msr.lo &= ~PIN_OPT_IDE;
wrmsr(MDD_PIN_OPT, msr);
}
msr = rdmsr(MDD_PIN_OPT);
printk_err("MDD_LBAR_FLSH0 is 0x%08x%08x\n", msr.hi,msr.lo);
msr = rdmsr(MDD_NANDF_DATA);
if (msr.lo != 0x01110111) {
printk_err("MDD_NANDF_DATA was 0x%08x%08x\n", msr.hi,msr.lo);
msr.lo = 0x01110111;
wrmsr(MDD_NANDF_DATA, msr);
}
msr = rdmsr(MDD_NANDF_DATA);
printk_err("MDD_NANDF_DATA is 0x%08x%08x\n", msr.hi,msr.lo);
msr = rdmsr(MDD_NADF_CNTL);
if (msr.lo != 0x0111) {
printk_err("MDD_NADF_CNTL was 0x%08x%08x\n", msr.hi,msr.lo);
msr.lo = 0x0111;
wrmsr(MDD_NADF_CNTL, msr);
}
msr = rdmsr(MDD_NADF_CNTL);
printk_err("MDD_NADF_CNTL is 0x%08x%08x\n", msr.hi,msr.lo);
printk_err("cs5536: EXIT %s\n", __FUNCTION__);
}
static void southbridge_enable(struct device *dev) static void southbridge_enable(struct device *dev)
{ {
struct southbridge_amd_cs5536_config *sb = (struct southbridge_amd_cs5536_config *)dev->chip_info; struct southbridge_amd_cs5536_config *sb = (struct southbridge_amd_cs5536_config *)dev->chip_info;
@ -48,7 +97,10 @@ static void southbridge_enable(struct device *dev)
outl(0x3081, GPIOL_INPUT_INVERT_ENABLE); outl(0x3081, GPIOL_INPUT_INVERT_ENABLE);
outl(GPIOL_0_SET, GPIO_MAPPER_X); outl(GPIOL_0_SET, GPIO_MAPPER_X);
} }
printk_err("%s: enable_ide_nand_flash is %d\n", __FUNCTION__, sb->enable_ide_nand_flash);
if (sb->enable_ide_nand_flash) {
enable_ide_nand_flash();
}
} }