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mb/google/volteer: Enable TCSS DMA0 for Volteer 

This explicitly enables TCSS DMA0 controller and disables
TBT PCIe2 and PCIE3 since they are unused on volteer.

BUG=🅱️146624360
TEST=Built and booted on Volteer.

Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I05cc9e3964d8037d433fca443be6e8d5b444bbce
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41387
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
John Zhao 2020-05-13 16:44:38 -07:00 committed by Furquan Shaikh
parent f219b6a2b9
commit 5d79a0cc5a
1 changed files with 5 additions and 6 deletions
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7
src/mainboard/google/volteer/variants/baseboard/devicetree.cb
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@ -132,7 +132,6 @@ chip soc/intel/tigerlake
register "IomTypeCPortPadCfg[6]" = "0x0"
register "IomTypeCPortPadCfg[7]" = "0x0"
# D3Hot and D3Cold for TCSS
register "TcssD3HotEnable" = "1"
register "TcssD3ColdEnable" = "1"
@ -229,14 +228,14 @@ chip soc/intel/tigerlake
device pci 06.0 off end # PEG60 0x9A09
device pci 07.0 on end # TBT_PCIe0 0x9A23
device pci 07.1 on end # TBT_PCIe1 0x9A25
device pci 07.2 on end # TBT_PCIe2 0x9A27
device pci 07.3 on end # TBT_PCIe3 0x9A29
device pci 07.2 off end # TBT_PCIe2 0x9A27
device pci 07.3 off end # TBT_PCIe3 0x9A29
device pci 08.0 on end # GNA 0x9A11
device pci 09.0 off end # NPK 0x9A33
device pci 0a.0 off end # Crash-log SRAM 0x9A0D
device pci 0d.0 on end # USB xHCI 0x9A13
device pci 0d.1 off end # USB xDCI (OTG) 0x9A15
device pci 0d.2 off end # TBT DMA0 0x9A1B
device pci 0d.2 on end # TBT DMA0 0x9A1B
device pci 0d.3 off end # TBT DMA1 0x9A1D
device pci 0e.0 off end # VMD 0x9A0B