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mediatek/mt8173: add APLL clock setting 

Add a new function mt_pll_set_aud_div() to set APLL for audio I2S.
The function is called by mainboard's configure_audio().

BRANCH=chromeos-2015.07
BUG=chrome-os-partner:41507
TEST=build and verified pass on oak board

Change-Id: Ia3c2f250627028422a7427b93d78d49545eb7a75
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: bb18943f5e74af7723bd4e01d4da96c0b153a0f6
Original-Change-Id: I7996a8048f2e54ab09093cca3c8bc7447b61170f
Original-Signed-off-by: Koro Chen <koro.chen@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/297225
Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13090
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Koro Chen 2015-08-04 16:16:46 +08:00 committed by Patrick Georgi
parent 0c22084ec0
commit 5d7c38ffa9
2 changed files with 35 additions and 0 deletions
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1
src/soc/mediatek/mt8173/include/soc/pll.h
View File

@ -283,5 +283,6 @@ enum {
void mt_pll_post_init(void); void mt_pll_post_init(void);
void mt_pll_init(void); void mt_pll_init(void);
void mt_pll_set_aud_div(u32 rate);
#endif /* SOC_MEDIATEK_MT8173_PLL_H */ #endif /* SOC_MEDIATEK_MT8173_PLL_H */

34
src/soc/mediatek/mt8173/pll.c
View File

@ -454,3 +454,37 @@ void mt_pll_post_init(void)
/* NOTICE: raise Vproc voltage before raise ARMPLL frequency */ /* NOTICE: raise Vproc voltage before raise ARMPLL frequency */
write32(&mt8173_infracfg->top_ckmuxsel, (1 << 2) | 1); write32(&mt8173_infracfg->top_ckmuxsel, (1 << 2) | 1);
} }
void mt_pll_set_aud_div(u32 rate)
{
u32 mclk_div;
u32 apll_clock = APLL2_CK_HZ;
int apll1 = 0;
if (rate % 11025 == 0) {
/* use APLL1 instead */
apll1 = 1;
apll_clock = APLL1_CK_HZ;
}
/* I2S1 clock */
mclk_div = (apll_clock / 256 / rate) - 1;
assert(apll_clock == rate * 256 * (mclk_div + 1));
if (apll1) {
/* mclk */
clrbits_le32(&mt8173_topckgen->clk_auddiv_0, 1 << 5);
clrsetbits_le32(&mt8173_topckgen->clk_auddiv_1, 0xff << 8,
mclk_div << 8);
/* bclk */
clrsetbits_le32(&mt8173_topckgen->clk_auddiv_0, 0xf << 24,
7 << 24);
} else {
/* mclk */
setbits_le32(&mt8173_topckgen->clk_auddiv_0, 1 << 5);
clrsetbits_le32(&mt8173_topckgen->clk_auddiv_2, 0xff << 8,
mclk_div << 8);
/* bclk */
clrsetbits_le32(&mt8173_topckgen->clk_auddiv_0, 0xf << 28,
7 << 28);
}
}