southbridge/amd/sb700: Add AHCI support
Change-Id: I147284e6a435f4b96d6821a122c1f4f9ddc2ea33 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11981 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Timothy Pearson
Stefan Reinauer
parent
45ded7df03
commit
5d7dc5545d
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@ -311,6 +311,8 @@
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#define PCI_DEVICE_ID_ATI_SB700_LPC 0x439D
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#define PCI_DEVICE_ID_ATI_SB700_SATA 0x4390
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#define PCI_DEVICE_ID_ATI_SB700_SATA_AHCI 0x4391
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#define PCI_DEVICE_ID_ATI_SB700_SATA_AHCI_AMD 0x4394
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#define PCI_DEVICE_ID_ATI_SB700_IDE 0x439C
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#define PCI_DEVICE_ID_ATI_SB700_HDA 0x4383
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#define PCI_DEVICE_ID_ATI_SB700_PCI 0x4384
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@ -42,6 +42,10 @@ config SOUTHBRIDGE_AMD_SB700_DISABLE_ISA_DMA
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bool
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default n
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config SOUTHBRIDGE_AMD_SB700_SATA_PORT_COUNT_BITFIELD
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hex
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default 0xf
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config EHCI_BAR
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hex
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default 0xfef00000
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@ -353,9 +353,13 @@ static void sb700_devices_por_init(void)
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{
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device_t dev;
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u8 byte;
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#if CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100
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u32 dword;
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#endif
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uint32_t dword;
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uint8_t nvram;
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uint8_t sata_ahci_mode;
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sata_ahci_mode = 0;
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if (get_option(&nvram, "sata_ahci_mode") == CB_SUCCESS)
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sata_ahci_mode = !!nvram;
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printk(BIOS_INFO, "sb700_devices_por_init()\n");
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/* SMBus Device, BDF:0-20-0 */
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@ -516,34 +520,56 @@ static void sb700_devices_por_init(void)
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/* Enable PCIB_DUAL_EN_UP will fix potential problem with PCI cards. */
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pci_write_config8(dev, 0x50, 0x01);
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if (!sata_ahci_mode){
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#if CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100
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/* SP5100 default SATA mode is RAID5 MODE */
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dev = pci_locate_device(PCI_ID(0x1002, 0x4393), 0);
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/* Set SATA Operation Mode, Set to IDE mode */
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byte = pci_read_config8(dev, 0x40);
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byte |= (1 << 0);
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pci_write_config8(dev, 0x40, byte);
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/* SP5100 default SATA mode is RAID5 MODE */
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dev = pci_locate_device(PCI_ID(0x1002, 0x4393), 0);
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dword = 0x01018f00;
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pci_write_config32(dev, 0x8, dword);
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/* Set SATA Operation Mode, Set to IDE mode */
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byte = pci_read_config8(dev, 0x40);
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byte |= (1 << 0);
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pci_write_config8(dev, 0x40, byte);
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/* set SATA Device ID writable */
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dword = pci_read_config32(dev, 0x40);
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dword &= ~(1 << 24);
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pci_write_config32(dev, 0x40, dword);
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dword = 0x01018f00;
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pci_write_config32(dev, 0x8, dword);
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/* set Device ID accommodate with IDE emulation mode configuration*/
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pci_write_config32(dev, 0x0, 0x43901002);
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/* set SATA Device ID writable */
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dword = pci_read_config32(dev, 0x40);
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dword &= ~(1 << 24);
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pci_write_config32(dev, 0x40, dword);
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/* rpr v2.13 4.17 Reset CPU on Sync Flood */
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abcfg_reg(0x10050, 1 << 2, 1 << 2);
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/* set Device ID consistent with IDE emulation mode configuration */
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pci_write_config32(dev, 0x0, 0x43901002);
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/* rpr v2.13 4.17 Reset CPU on Sync Flood */
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abcfg_reg(0x10050, 1 << 2, 1 << 2);
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#endif
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}
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/* SATA Device, BDF:0-17-0, Non-Raid-5 SATA controller */
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printk(BIOS_INFO, "sb700_devices_por_init(): SATA Device, BDF:0-18-0\n");
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printk(BIOS_INFO, "sb700_devices_por_init(): SATA Device, BDF:0-17-0\n");
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dev = pci_locate_device(PCI_ID(0x1002, 0x4390), 0);
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/*PHY Global Control*/
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if (sata_ahci_mode) {
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/* Switch to AHCI mode (AMD inbox) */
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dword = pci_read_config32(dev, 0x40);
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dword |= (0x1 << 24); /* Lock Flash Device ID = 1 */
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pci_write_config32(dev, 0x40, dword);
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/* Deactivate Sub-Class Code write protection */
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byte = pci_read_config8(dev, 0x40);
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byte |= (1 << 0);
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pci_write_config8(dev, 0x40, byte);
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dword = pci_read_config32(dev, 0x08);
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dword &= ~(0xff << 16); /* Sub-Class Code = 0x6 */
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dword |= (0x6 << 16);
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dword &= ~(0xff << 8); /* Operating Mode Selection = 0x1 */
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dword |= (0x1 << 8);
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pci_write_config32(dev, 0x08, dword);
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}
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/* PHY Global Control */
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pci_write_config16(dev, 0x86, 0x2C00);
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}
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@ -675,6 +701,11 @@ static void sb700_pci_cfg(void)
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/* SATA Device, BDF:0-17-0, Non-Raid-5 SATA controller */
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dev = pci_locate_device(PCI_ID(0x1002, 0x4390), 0);
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if (dev == PCI_DEV_INVALID)
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dev = pci_locate_device(PCI_ID(0x1002, 0x4391), 0);
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if (dev == PCI_DEV_INVALID)
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dev = pci_locate_device(PCI_ID(0x1002, 0x4394), 0);
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/* rpr7.12 SATA MSI and D3 Power State Capability. */
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byte = pci_read_config8(dev, 0x40);
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byte |= 1 << 0;
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@ -1,6 +1,7 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
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* Copyright (C) 2010 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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@ -18,6 +19,7 @@
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <device/pci_ops.h>
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#include <option.h>
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#include "sb700.h"
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static void ide_init(struct device *dev)
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@ -26,6 +28,12 @@ static void ide_init(struct device *dev)
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/* Enable ide devices so the linux ide driver will work */
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u32 dword;
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u8 byte;
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uint8_t nvram;
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uint8_t sata_ahci_mode;
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sata_ahci_mode = 0;
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if (get_option(&nvram, "sata_ahci_mode") == CB_SUCCESS)
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sata_ahci_mode = !!nvram;
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conf = dev->chip_info;
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@ -35,25 +43,25 @@ static void ide_init(struct device *dev)
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dword &= ~(1 << 16);
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pci_write_config32(dev, 0x70, dword);
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/* Enable UDMA on all devices, it will become UDMA0 (default PIO is PIO0) */
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byte = pci_read_config8(dev, 0x54);
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byte |= 0xf;
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pci_write_config8(dev, 0x54, byte);
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if (!sata_ahci_mode) {
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/* Enable UDMA on all devices, it will become UDMA0 (default PIO is PIO0) */
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byte = pci_read_config8(dev, 0x54);
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byte |= 0xf;
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pci_write_config8(dev, 0x54, byte);
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/* Enable I/O Access&& Bus Master */
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dword = pci_read_config16(dev, 0x4);
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dword |= 1 << 2;
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pci_write_config16(dev, 0x4, dword);
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/* Enable I/O Access&& Bus Master */
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dword = pci_read_config16(dev, 0x4);
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dword |= 1 << 2;
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pci_write_config16(dev, 0x4, dword);
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/* set ide as primary, if you want to boot from IDE, you'd better set it
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* in $vendor/$mainboard/devicetree.cb */
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if (conf->boot_switch_sata_ide == 1) {
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struct device *sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
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byte = pci_read_config8(sm_dev, 0xAD);
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byte |= 1 << 4;
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pci_write_config8(sm_dev, 0xAD, byte);
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/* set ide as primary, if you want to boot from IDE, you'd better set it
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* in $vendor/$mainboard/devicetree.cb */
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if (conf->boot_switch_sata_ide == 1) {
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struct device *sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
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byte = pci_read_config8(sm_dev, 0xad);
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byte |= 1 << 4;
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pci_write_config8(sm_dev, 0xad, byte);
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}
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}
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}
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@ -2,6 +2,7 @@
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2010 Advanced Micro Devices, Inc.
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* Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -20,18 +21,19 @@
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#include <device/pci_ids.h>
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#include <device/pci_ops.h>
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#include <arch/io.h>
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#include <option.h>
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#include "sb700.h"
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static int sata_drive_detect(int portnum, u16 iobar)
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static int sata_drive_detect(int portnum, uint16_t iobar)
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{
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u8 byte, byte2;
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int i = 0;
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outb(0xA0 + 0x10 * (portnum % 2), iobar + 0x6);
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outb(0xa0 + 0x10 * (portnum % 2), iobar + 0x6);
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while (byte = inb(iobar + 0x6), byte2 = inb(iobar + 0x7),
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(byte != (0xA0 + 0x10 * (portnum % 2))) ||
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(byte != (0xa0 + 0x10 * (portnum % 2))) ||
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((byte2 & 0x88) != 0)) {
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printk(BIOS_SPEW, "0x6=%x, 0x7=%x\n", byte, byte2);
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if (byte != (0xA0 + 0x10 * (portnum % 2))) {
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if (byte != (0xa0 + 0x10 * (portnum % 2))) {
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/* This will happen at the first iteration of this loop
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* if the first SATA port is unpopulated and the
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* second SATA port is populated.
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@ -61,15 +63,15 @@ void __attribute__((weak)) sb7xx_51xx_setup_sata_phys(struct device *dev)
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pci_write_config32(dev, 0x90, 0x01B48016);
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pci_write_config32(dev, 0x94, 0x01B48016);
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pci_write_config32(dev, 0x98, 0x01B48016);
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pci_write_config32(dev, 0x9C, 0x01B48016);
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pci_write_config32(dev, 0x9c, 0x01B48016);
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/* RPR7.6.3 SATA GEN II PHY port setting for port [0~5]. */
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pci_write_config16(dev, 0xA0, 0xA09A);
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pci_write_config16(dev, 0xA2, 0xA09F);
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pci_write_config16(dev, 0xA4, 0xA07A);
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pci_write_config16(dev, 0xA6, 0xA07A);
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pci_write_config16(dev, 0xA8, 0xA07A);
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pci_write_config16(dev, 0xAA, 0xA07A);
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pci_write_config16(dev, 0xa0, 0xA09A);
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pci_write_config16(dev, 0xa2, 0xA09F);
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pci_write_config16(dev, 0xa4, 0xA07A);
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pci_write_config16(dev, 0xa6, 0xA07A);
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pci_write_config16(dev, 0xa8, 0xA07A);
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pci_write_config16(dev, 0xaa, 0xA07A);
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}
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static void sata_init(struct device *dev)
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@ -79,8 +81,18 @@ static void sata_init(struct device *dev)
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u32 dword;
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u8 rev_id;
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void *sata_bar5;
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u16 sata_bar0, sata_bar1, sata_bar2, sata_bar3, sata_bar4;
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uint16_t sata_bar0, sata_bar1, sata_bar2, sata_bar3, sata_bar4;
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uint16_t ide_bar0, ide_bar1, ide_bar2, ide_bar3;
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uint16_t current_bar;
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int i, j;
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uint8_t nvram;
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uint8_t sata_ahci_mode;
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uint8_t port_count;
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uint8_t max_port_count;
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sata_ahci_mode = 0;
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if (get_option(&nvram, "sata_ahci_mode") == CB_SUCCESS)
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sata_ahci_mode = !!nvram;
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device_t sm_dev;
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/* SATA SMBus Disable */
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@ -94,21 +106,39 @@ static void sata_init(struct device *dev)
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byte |= (1 << 5);
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pci_write_config8(sm_dev, 0xad, byte);
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/* get rev_id */
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rev_id = pci_read_config8(sm_dev, 0x08) - 0x28;
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if (sata_ahci_mode) {
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/* Enable link latency enhancement on A14 and above */
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if (rev_id >= 0x14) {
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byte = pci_read_config8(sm_dev, 0xad);
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byte &= ~(1 << 5);
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pci_write_config8(sm_dev, 0xad, byte);
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}
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}
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/* Disable combined mode */
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byte = pci_read_config8(sm_dev, 0xad);
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byte &= ~(1 << 3);
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pci_write_config8(sm_dev, 0xad, byte);
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device_t ide_dev;
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/* IDE Device */
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ide_dev = dev_find_slot(0, PCI_DEVFN(0x14, 1));
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/* RPR 7.2 SATA Initialization */
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/* Set the interrupt Mapping to INTG# */
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byte = pci_read_config8(sm_dev, 0xaf);
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byte = 0x6 << 2;
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pci_write_config8(sm_dev, 0xaf, byte);
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/* get rev_id */
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rev_id = pci_read_config8(sm_dev, 0x08) - 0x28;
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/* get base address */
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sata_bar5 = (void *)(pci_read_config32(dev, 0x24) & ~0x3FF);
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sata_bar0 = pci_read_config16(dev, 0x10) & ~0x7;
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sata_bar1 = pci_read_config16(dev, 0x14) & ~0x3;
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sata_bar2 = pci_read_config16(dev, 0x18) & ~0x7;
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sata_bar3 = pci_read_config16(dev, 0x1C) & ~0x3;
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sata_bar3 = pci_read_config16(dev, 0x1c) & ~0x3;
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sata_bar4 = pci_read_config16(dev, 0x20) & ~0xf;
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printk(BIOS_SPEW, "sata_bar0=%x\n", sata_bar0); /* 3030 */
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@ -118,11 +148,16 @@ static void sata_init(struct device *dev)
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printk(BIOS_SPEW, "sata_bar4=%x\n", sata_bar4); /* 3000 */
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printk(BIOS_SPEW, "sata_bar5=%p\n", sata_bar5); /* e0309000 */
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/* disable combined mode */
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byte = pci_read_config8(sm_dev, 0xAD);
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byte &= ~(1 << 3);
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pci_write_config8(sm_dev, 0xAD, byte);
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/* Program the 2C to 0x43801002 */
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ide_bar0 = pci_read_config16(ide_dev, 0x10) & ~0x7;
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ide_bar1 = pci_read_config16(ide_dev, 0x14) & ~0x3;
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ide_bar2 = pci_read_config16(ide_dev, 0x18) & ~0x7;
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ide_bar3 = pci_read_config16(ide_dev, 0x1c) & ~0x3;
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printk(BIOS_SPEW, "ide_bar0=%x\n", ide_bar0);
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printk(BIOS_SPEW, "ide_bar1=%x\n", ide_bar1);
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printk(BIOS_SPEW, "ide_bar2=%x\n", ide_bar2);
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printk(BIOS_SPEW, "ide_bar3=%x\n", ide_bar3);
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/* Program the Subsystem ID/VID to 0x43801002 */
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dword = 0x43801002;
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pci_write_config32(dev, 0x2c, dword);
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@ -136,15 +171,48 @@ static void sata_init(struct device *dev)
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byte |= (1 << 2);
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pci_write_config8(dev, 0x40, byte);
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/* Set SATA Operation Mode, Set to IDE mode */
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/* Unlock subclass and certain BAR R/O registers */
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byte = pci_read_config8(dev, 0x40);
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byte |= (1 << 0);
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byte |= (1 << 4);
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pci_write_config8(dev, 0x40, byte);
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dword = 0x01018f00;
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pci_write_config32(dev, 0x8, dword);
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/* Disable AHCI enhancement (AMD SP5100 RPR page 54) */
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dword = pci_read_config32(dev, 0x40);
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dword |= (1 << 23);
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pci_write_config32(dev, 0x40, dword);
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if (sata_ahci_mode) {
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/* Force number of ports to 6
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* NOTE: This is not documented in the register
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* reference guide, but CIMX needs to do this
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* to activate all 6 ports when IDE is disabled.
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*/
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dword = read32(sata_bar5 + 0x00);
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dword &= ~0x7;
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dword |= 0x5;
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write32(sata_bar5 + 0x00, dword);
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} else {
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/* Set SATA Operation Mode, Set to IDE mode */
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byte = pci_read_config8(dev, 0x40);
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byte |= (1 << 4);
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pci_write_config8(dev, 0x40, byte);
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dword = 0x01018f00;
|
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pci_write_config32(dev, 0x8, dword);
|
||||
}
|
||||
|
||||
/* Get maximum number of ports */
|
||||
max_port_count = read32(sata_bar5 + 0x00) & 0x1f;
|
||||
max_port_count++;
|
||||
printk(BIOS_SPEW, "Maximum SATA port count supported by silicon: %d\n", max_port_count);
|
||||
|
||||
/* Set number of ports */
|
||||
dword = CONFIG_SOUTHBRIDGE_AMD_SB700_SATA_PORT_COUNT_BITFIELD;
|
||||
for (i = max_port_count; i < 32; i++)
|
||||
dword &= ~(0x1 << i);
|
||||
write32(sata_bar5 + 0x0c, dword);
|
||||
|
||||
/* Write protect Sub-Class Code */
|
||||
byte = pci_read_config8(dev, 0x40);
|
||||
byte &= ~(1 << 0);
|
||||
pci_write_config8(dev, 0x40, byte);
|
||||
|
|
@ -177,6 +245,7 @@ static void sata_init(struct device *dev)
|
|||
byte = 0x10;
|
||||
pci_write_config8(dev, 0x46, byte);
|
||||
sb7xx_51xx_setup_sata_phys(dev);
|
||||
|
||||
/* Enable the I/O, MM, BusMaster access for SATA */
|
||||
byte = pci_read_config8(dev, 0x4);
|
||||
byte |= 7 << 0;
|
||||
|
|
@ -187,62 +256,75 @@ static void sata_init(struct device *dev)
|
|||
pci_write_config32(dev, 0xC, 0x00004000);
|
||||
#endif
|
||||
|
||||
/* RPR7.7 SATA drive detection. */
|
||||
/* Use BAR5+0x128,BAR0 for Primary Slave */
|
||||
/* Use BAR5+0x1A8,BAR0 for Primary Slave */
|
||||
/* Use BAR5+0x228,BAR2 for Secondary Master */
|
||||
/* Use BAR5+0x2A8,BAR2 for Secondary Slave */
|
||||
/* Use BAR5+0x328,PATA_BAR0/2 for Primary/Secondary master emulation */
|
||||
/* Use BAR5+0x3A8,PATA_BAR0/2 for Primary/Secondary Slave emulation */
|
||||
/* Determine port count */
|
||||
port_count = 0;
|
||||
for (i = 0; i < 32; i++) {
|
||||
if (CONFIG_SOUTHBRIDGE_AMD_SB700_SATA_PORT_COUNT_BITFIELD & (0x1 << i))
|
||||
port_count = i;
|
||||
}
|
||||
port_count++;
|
||||
if (port_count > max_port_count)
|
||||
port_count = max_port_count;
|
||||
|
||||
/* TODO: port 4,5, which are PATA emulations. What are PATA_BARs? */
|
||||
|
||||
for (i = 0; i < 4; i++) {
|
||||
byte = read8(sata_bar5 + 0x128 + 0x80 * i);
|
||||
printk(BIOS_SPEW, "SATA port %i status = %x\n", i, byte);
|
||||
byte &= 0xF;
|
||||
if( byte == 0x1 ) {
|
||||
/* If the drive status is 0x1 then we see it but we aren't talking to it. */
|
||||
/* Try to do something about it. */
|
||||
printk(BIOS_SPEW, "SATA device detected but not talking. Trying lower speed.\n");
|
||||
|
||||
/* Read in Port-N Serial ATA Control Register */
|
||||
byte = read8(sata_bar5 + 0x12C + 0x80 * i);
|
||||
|
||||
/* Set Reset Bit and 1.5g bit */
|
||||
byte |= 0x11;
|
||||
write8((sata_bar5 + 0x12C + 0x80 * i), byte);
|
||||
|
||||
/* Wait 1ms */
|
||||
mdelay(1);
|
||||
|
||||
/* Clear Reset Bit */
|
||||
byte &= ~0x01;
|
||||
write8((sata_bar5 + 0x12C + 0x80 * i), byte);
|
||||
|
||||
/* Wait 1ms */
|
||||
mdelay(1);
|
||||
|
||||
/* Reread status */
|
||||
if (!sata_ahci_mode) {
|
||||
/* RPR7.7 SATA drive detection. */
|
||||
/* Use BAR5+0x128,BAR0 for Primary Slave */
|
||||
/* Use BAR5+0x1A8,BAR0 for Primary Slave */
|
||||
/* Use BAR5+0x228,BAR2 for Secondary Master */
|
||||
/* Use BAR5+0x2A8,BAR2 for Secondary Slave */
|
||||
/* Use BAR5+0x328,PATA_BAR0/2 for Primary/Secondary Master emulation */
|
||||
/* Use BAR5+0x3A8,PATA_BAR0/2 for Primary/Secondary Slave emulation */
|
||||
for (i = 0; i < port_count; i++) {
|
||||
byte = read8(sata_bar5 + 0x128 + 0x80 * i);
|
||||
printk(BIOS_SPEW, "SATA port %i status = %x\n", i, byte);
|
||||
byte &= 0xF;
|
||||
}
|
||||
if (byte == 0x1) {
|
||||
/* If the drive status is 0x1 then we see it but we aren't talking to it. */
|
||||
/* Try to do something about it. */
|
||||
printk(BIOS_SPEW, "SATA device detected but not talking. Trying lower speed.\n");
|
||||
|
||||
if (byte == 0x3) {
|
||||
for (j = 0; j < 10; j++) {
|
||||
if (!sata_drive_detect(i, ((i / 2) == 0) ? sata_bar0 : sata_bar2))
|
||||
break;
|
||||
/* Read in Port-N Serial ATA Control Register */
|
||||
byte = read8(sata_bar5 + 0x12C + 0x80 * i);
|
||||
|
||||
/* Set Reset Bit and 1.5g bit */
|
||||
byte |= 0x11;
|
||||
write8((sata_bar5 + 0x12C + 0x80 * i), byte);
|
||||
|
||||
/* Wait 1ms */
|
||||
mdelay(1);
|
||||
|
||||
/* Clear Reset Bit */
|
||||
byte &= ~0x01;
|
||||
write8((sata_bar5 + 0x12C + 0x80 * i), byte);
|
||||
|
||||
/* Wait 1ms */
|
||||
mdelay(1);
|
||||
|
||||
/* Reread status */
|
||||
byte = read8(sata_bar5 + 0x128 + 0x80 * i);
|
||||
printk(BIOS_SPEW, "SATA port %i status = %x\n", i, byte);
|
||||
byte &= 0xF;
|
||||
}
|
||||
|
||||
if (byte == 0x3) {
|
||||
for (j = 0; j < 10; j++) {
|
||||
if (i < 4)
|
||||
current_bar = ((i / 2) == 0) ? sata_bar0 : sata_bar2;
|
||||
else
|
||||
current_bar = ide_bar0;
|
||||
if (!sata_drive_detect(i, current_bar))
|
||||
break;
|
||||
}
|
||||
printk(BIOS_DEBUG, "%s %s device is %sready after %i tries\n",
|
||||
(i / 2) ? "Secondary" : "Primary",
|
||||
(i % 2 ) ? "Slave" : "Master",
|
||||
(j == 10) ? "not " : "",
|
||||
(j == 10) ? j : j + 1);
|
||||
} else {
|
||||
printk(BIOS_DEBUG, "No %s %s SATA drive on Slot%i\n",
|
||||
(i / 2) ? "Secondary" : "Primary",
|
||||
(i % 2 ) ? "Slave" : "Master", i);
|
||||
}
|
||||
printk(BIOS_DEBUG, "%s %s device is %sready after %i tries\n",
|
||||
(i / 2) ? "Secondary" : "Primary",
|
||||
(i % 2 ) ? "Slave" : "Master",
|
||||
(j == 10) ? "not " : "",
|
||||
(j == 10) ? j : j + 1);
|
||||
} else {
|
||||
printk(BIOS_DEBUG, "No %s %s SATA drive on Slot%i\n",
|
||||
(i / 2) ? "Secondary" : "Primary",
|
||||
(i % 2 ) ? "Slave" : "Master", i);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -252,13 +334,15 @@ static void sata_init(struct device *dev)
|
|||
byte |= 1 << 1;
|
||||
write8((sata_bar5 + 0x4), byte);
|
||||
|
||||
/* Clear error status */
|
||||
write32((sata_bar5 + 0x130), 0xFFFFFFFF);
|
||||
write32((sata_bar5 + 0x1b0), 0xFFFFFFFF);
|
||||
write32((sata_bar5 + 0x230), 0xFFFFFFFF);
|
||||
write32((sata_bar5 + 0x2b0), 0xFFFFFFFF);
|
||||
write32((sata_bar5 + 0x330), 0xFFFFFFFF);
|
||||
write32((sata_bar5 + 0x3b0), 0xFFFFFFFF);
|
||||
if (!sata_ahci_mode) {
|
||||
/* Clear error status */
|
||||
write32((sata_bar5 + 0x130), 0xFFFFFFFF);
|
||||
write32((sata_bar5 + 0x1b0), 0xFFFFFFFF);
|
||||
write32((sata_bar5 + 0x230), 0xFFFFFFFF);
|
||||
write32((sata_bar5 + 0x2b0), 0xFFFFFFFF);
|
||||
write32((sata_bar5 + 0x330), 0xFFFFFFFF);
|
||||
write32((sata_bar5 + 0x3b0), 0xFFFFFFFF);
|
||||
}
|
||||
|
||||
/* Clear SATA status,Firstly we get the AcpiGpe0BlkAddr */
|
||||
/* ????? why CIM does not set the AcpiGpe0BlkAddr , but use it??? */
|
||||
|
|
@ -289,3 +373,15 @@ static const struct pci_driver sata0_driver __pci_driver = {
|
|||
.vendor = PCI_VENDOR_ID_ATI,
|
||||
.device = PCI_DEVICE_ID_ATI_SB700_SATA,
|
||||
};
|
||||
|
||||
static const struct pci_driver sata1_driver __pci_driver = {
|
||||
.ops = &sata_ops,
|
||||
.vendor = PCI_VENDOR_ID_ATI,
|
||||
.device = PCI_DEVICE_ID_ATI_SB700_SATA_AHCI,
|
||||
};
|
||||
|
||||
static const struct pci_driver sata2_driver __pci_driver = {
|
||||
.ops = &sata_ops,
|
||||
.vendor = PCI_VENDOR_ID_ATI,
|
||||
.device = PCI_DEVICE_ID_ATI_SB700_SATA_AHCI_AMD,
|
||||
};
|
||||
|
|
|
|||
Loading…
Reference in New Issue