cheza: Add board reset via Chrome EC
This patch implements board reset on the Cheza board. The real board reset used by the operating system uses the PMIC, but unfortunately the PMIC needs to be configured right for that to work. The PMIC configuration currently happens in the Qualcomm blob (QcLib) that is run from romstage, but vboot needs to be able to reboot during verstage already. Porting all the PMIC initialization code to run in the bootblock seems excessive (and at odds with the goal of doing as little as possible before verification), so we'll just do a little hack and ask the EC to perform a cold reset instead. For vboot purposes, this should work just as well. BUG=b:118501305 TEST=Hacked vboot code to call vboot_reboot(), confirmed that board reset and came back up as expected. Change-Id: I3858d95f481884a87c243d4fa3d6369c1e8a5a2c Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/29849 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -16,7 +16,6 @@ config BOARD_SPECIFIC_OPTIONS
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select SPI_FLASH
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select SPI_FLASH
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select SPI_FLASH_WINBOND
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select SPI_FLASH_WINBOND
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select MAINBOARD_HAS_CHROMEOS
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select MAINBOARD_HAS_CHROMEOS
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select MISSING_BOARD_RESET
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select MAINBOARD_HAS_TPM2
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select MAINBOARD_HAS_TPM2
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select MAINBOARD_HAS_SPI_TPM_CR50
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select MAINBOARD_HAS_SPI_TPM_CR50
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@ -17,17 +17,21 @@ bootblock-y += boardid.c
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bootblock-y += memlayout.ld
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bootblock-y += memlayout.ld
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bootblock-y += chromeos.c
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bootblock-y += chromeos.c
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bootblock-y += bootblock.c
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bootblock-y += bootblock.c
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bootblock-y += reset.c
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verstage-y += boardid.c
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verstage-y += boardid.c
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verstage-y += memlayout.ld
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verstage-y += memlayout.ld
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verstage-y += chromeos.c
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verstage-y += chromeos.c
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verstage-y += reset.c
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romstage-y += boardid.c
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romstage-y += boardid.c
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romstage-y += memlayout.ld
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romstage-y += memlayout.ld
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romstage-y += chromeos.c
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romstage-y += chromeos.c
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romstage-y += romstage.c
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romstage-y += romstage.c
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romstage-y += reset.c
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ramstage-y += boardid.c
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ramstage-y += boardid.c
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ramstage-y += memlayout.ld
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ramstage-y += memlayout.ld
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ramstage-y += chromeos.c
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ramstage-y += chromeos.c
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ramstage-y += mainboard.c
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ramstage-y += mainboard.c
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ramstage-y += reset.c
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@ -0,0 +1,24 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2018 Google LLC
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <ec/google/chromeec/ec.h>
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#include <reset.h>
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/* Can't do a "real" reset before the PMIC is initialized in QcLib (romstage),
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but this works well enough for our purposes. */
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void do_board_reset(void)
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{
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google_chromeec_reboot(0, EC_REBOOT_COLD, 0);
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}
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