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mb/google/brya: Set same size for CSE_RW, ME_RW_A and ME_RW_B 

CSE RW firmware from ME_RW_A/ME_RW_B is copied over to CSE_RW region
in case of firmware update. Ensure that the size of the regions match
so that we do not have situations where ME_RW_A/B firmware grows
bigger than what CSE_RW can hold.

BUG=b:189177538

Change-Id: I374db5d490292eeb98f67dc684c2106d42779dac
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58213
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Furquan Shaikh 2021-10-14 10:02:51 -07:00
parent 3f0d64329c
commit 5d8f4badda
1 changed files with 2 additions and 2 deletions
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4
src/mainboard/google/brya/chromeos.fmd
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@ -14,7 +14,7 @@ FLASH 32M {
VBLOCK_A 64K VBLOCK_A 64K
FW_MAIN_A(CBFS) FW_MAIN_A(CBFS)
RW_FWID_A 64 RW_FWID_A 64
ME_RW_A(CBFS) 3M ME_RW_A(CBFS) 3008K
} }
RW_LEGACY(CBFS) 2M RW_LEGACY(CBFS) 2M
RW_MISC 1M { RW_MISC 1M {
@ -43,7 +43,7 @@ FLASH 32M {
VBLOCK_B 64K VBLOCK_B 64K
FW_MAIN_B(CBFS) FW_MAIN_B(CBFS)
RW_FWID_B 64 RW_FWID_B 64
ME_RW_B(CBFS) 3M ME_RW_B(CBFS) 3008K
} }
# Make WP_RO region align with SPI vendor # Make WP_RO region align with SPI vendor
# memory protected range specification. # memory protected range specification.