soc/intel: Drop bootblock_cpu_init() function

Just call `fast_spi_cache_bios_region()` directly instead.

Change-Id: I99f6ed4cf1a5c49b078cfd05e357c2d4c26ade45
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50952
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/intel/alderlake/Makefile.inc

@@ -15,7 +15,6 @@ all-y += spi.c
 all-y += uart.c
 
 bootblock-y += bootblock/bootblock.c
-bootblock-y += bootblock/cpu.c
 bootblock-y += bootblock/pch.c
 bootblock-y += bootblock/report_platform.c
 bootblock-y += espi.c

src/soc/intel/alderlake/bootblock/bootblock.c

@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <bootblock_common.h>
+#include <intelblocks/fast_spi.h>
 #include <intelblocks/systemagent.h>
 #include <intelblocks/tco.h>
 #include <intelblocks/uart.h>
@@ -16,7 +17,7 @@ void bootblock_soc_early_init(void)
 {
 	bootblock_systemagent_early_init();
 	bootblock_pch_early_init();
-	bootblock_cpu_init();
+	fast_spi_cache_bios_region();
 	pch_early_iorange_init();
 	if (CONFIG(INTEL_LPSS_UART_FOR_CONSOLE))
 		uart_bootblock_init();

src/soc/intel/alderlake/bootblock/cpu.c

@@ -1,20 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/*
- * This file is created based on Intel Alder Lake Processor PCH Datasheet
- * Document number: 621483
- * Chapter number: 7
- */
-
-#include <intelblocks/fast_spi.h>
-#include <soc/bootblock.h>
-
-void bootblock_cpu_init(void)
-{
-	/*
-	 * Alderlake platform doesn't support booting from any other media
-	 * than SPI flash and on IA platform SPI is memory mapped hence
-	 * enabling temporary caching of memory-mapped spi boot media.
-	 */
-	fast_spi_cache_bios_region();
-}

src/soc/intel/alderlake/include/soc/bootblock.h

@@ -4,7 +4,6 @@
 #define _SOC_ALDERLAKE_BOOTBLOCK_H_
 
 /* Bootblock pre console init programming */
-void bootblock_cpu_init(void);
 void bootblock_pch_early_init(void);
 
 /* Bootblock post console init programming */

src/soc/intel/cannonlake/Makefile.inc

@@ -10,7 +10,6 @@ subdirs-y += ../../../cpu/x86/tsc
 subdirs-y += ../../../cpu/intel/common
 
 bootblock-y += bootblock/bootblock.c
-bootblock-y += bootblock/cpu.c
 bootblock-y += bootblock/pch.c
 bootblock-y += pmutil.c
 bootblock-y += bootblock/report_platform.c

src/soc/intel/cannonlake/bootblock/bootblock.c

@@ -2,6 +2,7 @@
 
 #include <bootblock_common.h>
 #include <cpu/x86/mtrr.h>
+#include <intelblocks/fast_spi.h>
 #include <intelblocks/gspi.h>
 #include <intelblocks/systemagent.h>
 #include <intelblocks/tco.h>
@@ -52,7 +53,7 @@ void bootblock_soc_early_init(void)
 {
 	bootblock_systemagent_early_init();
 	bootblock_pch_early_init();
-	bootblock_cpu_init();
+	fast_spi_cache_bios_region();
 	pch_early_iorange_init();
 	if (CONFIG(INTEL_LPSS_UART_FOR_CONSOLE))
 		uart_bootblock_init();

src/soc/intel/cannonlake/bootblock/cpu.c

@@ -1,10 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <intelblocks/fast_spi.h>
-#include <soc/bootblock.h>
-
-void bootblock_cpu_init(void)
-{
-	/* Temporarily cache the memory-mapped boot media. */
-	fast_spi_cache_bios_region();
-}

src/soc/intel/cannonlake/include/soc/bootblock.h

@@ -4,7 +4,6 @@
 #define _SOC_CANNONLAKE_BOOTBLOCK_H_
 
 /* Bootblock pre console init programming */
-void bootblock_cpu_init(void);
 void bootblock_pch_early_init(void);
 
 /* Bootblock post console init programming */

src/soc/intel/elkhartlake/Makefile.inc

@@ -16,7 +16,6 @@ all-y += spi.c
 all-y += uart.c
 
 bootblock-y += bootblock/bootblock.c
-bootblock-y += bootblock/cpu.c
 bootblock-y += bootblock/pch.c
 bootblock-y += bootblock/report_platform.c
 bootblock-y += espi.c

src/soc/intel/elkhartlake/bootblock/bootblock.c

@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <bootblock_common.h>
+#include <intelblocks/fast_spi.h>
 #include <intelblocks/systemagent.h>
 #include <intelblocks/tco.h>
 #include <intelblocks/uart.h>
@@ -16,7 +17,7 @@ void bootblock_soc_early_init(void)
 {
 	bootblock_systemagent_early_init();
 	bootblock_pch_early_init();
-	bootblock_cpu_init();
+	fast_spi_cache_bios_region();
 	pch_early_iorange_init();
 	if (CONFIG(INTEL_LPSS_UART_FOR_CONSOLE))
 		uart_bootblock_init();

src/soc/intel/elkhartlake/bootblock/cpu.c

@@ -1,15 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <intelblocks/fast_spi.h>
-#include <soc/bootblock.h>
-
-void bootblock_cpu_init(void)
-{
-	/*
-	 * Elkhartlake platform doesn't support booting from any other media
-	 * (like eMMC on APL/GLK platform) than only booting from SPI device
-	 * and on IA platform SPI is memory mapped hence enabling temporarily
-	 * caching on memory-mapped spi boot media.
-	 */
-	fast_spi_cache_bios_region();
-}

src/soc/intel/elkhartlake/include/soc/bootblock.h

@@ -4,7 +4,6 @@
 #define _SOC_ELKHARTLAKE_BOOTBLOCK_H_
 
 /* Bootblock pre console init programming */
-void bootblock_cpu_init(void);
 void bootblock_pch_early_init(void);
 
 /* Bootblock post console init programming */

src/soc/intel/icelake/Makefile.inc

@@ -16,7 +16,6 @@ all-y += spi.c
 all-y += uart.c
 
 bootblock-y += bootblock/bootblock.c
-bootblock-y += bootblock/cpu.c
 bootblock-y += bootblock/pch.c
 bootblock-y += bootblock/report_platform.c
 bootblock-y += espi.c

src/soc/intel/icelake/bootblock/bootblock.c

@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <bootblock_common.h>
+#include <intelblocks/fast_spi.h>
 #include <intelblocks/systemagent.h>
 #include <intelblocks/tco.h>
 #include <intelblocks/uart.h>
@@ -16,7 +17,7 @@ void bootblock_soc_early_init(void)
 {
 	bootblock_systemagent_early_init();
 	bootblock_pch_early_init();
-	bootblock_cpu_init();
+	fast_spi_cache_bios_region();
 	pch_early_iorange_init();
 	if (CONFIG(INTEL_LPSS_UART_FOR_CONSOLE))
 		uart_bootblock_init();

src/soc/intel/icelake/bootblock/cpu.c

@@ -1,18 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <intelblocks/fast_spi.h>
-#include <soc/bootblock.h>
-
-void bootblock_cpu_init(void)
-{
-	/*
-	 * Icelake platform doesn't support booting from any other media
-	 * (like eMMC on APL/GLK platform) than only booting from SPI device
-	 * and on IA platform SPI is memory mapped hence enabling temporarily
-	 * cacheing on memory-mapped spi boot media.
-	 *
-	 * This assumption will not hold good for APL/GLK platform where boot
-	 * from eMMC is also possible options.
-	 */
-	fast_spi_cache_bios_region();
-}

src/soc/intel/icelake/include/soc/bootblock.h

@@ -4,7 +4,6 @@
 #define _SOC_ICELAKE_BOOTBLOCK_H_
 
 /* Bootblock pre console init programming */
-void bootblock_cpu_init(void);
 void bootblock_pch_early_init(void);
 
 /* Bootblock post console init programming */

src/soc/intel/jasperlake/Makefile.inc

@@ -16,7 +16,6 @@ all-y += spi.c
 all-y += uart.c
 
 bootblock-y += bootblock/bootblock.c
-bootblock-y += bootblock/cpu.c
 bootblock-y += bootblock/pch.c
 bootblock-y += bootblock/report_platform.c
 bootblock-y += espi.c

src/soc/intel/jasperlake/bootblock/bootblock.c

@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <bootblock_common.h>
+#include <intelblocks/fast_spi.h>
 #include <intelblocks/systemagent.h>
 #include <intelblocks/tco.h>
 #include <intelblocks/uart.h>
@@ -16,7 +17,7 @@ void bootblock_soc_early_init(void)
 {
 	bootblock_systemagent_early_init();
 	bootblock_pch_early_init();
-	bootblock_cpu_init();
+	fast_spi_cache_bios_region();
 	pch_early_iorange_init();
 	if (CONFIG(INTEL_LPSS_UART_FOR_CONSOLE))
 		uart_bootblock_init();

src/soc/intel/jasperlake/bootblock/cpu.c

@@ -1,18 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <intelblocks/fast_spi.h>
-#include <soc/bootblock.h>
-
-void bootblock_cpu_init(void)
-{
-	/*
-	 * Jasperlake platform doesn't support booting from any other media
-	 * (like eMMC on APL/GLK platform) than only booting from SPI device
-	 * and on IA platform SPI is memory mapped hence enabling temporarily
-	 * cacheing on memory-mapped spi boot media.
-	 *
-	 * This assumption will not hold good for APL/GLK platform where boot
-	 * from eMMC is also possible options.
-	 */
-	fast_spi_cache_bios_region();
-}

src/soc/intel/jasperlake/include/soc/bootblock.h

@@ -4,7 +4,6 @@
 #define _SOC_JASPERLAKE_BOOTBLOCK_H_
 
 /* Bootblock pre console init programming */
-void bootblock_cpu_init(void);
 void bootblock_pch_early_init(void);
 
 /* Bootblock post console init programming */

src/soc/intel/skylake/Makefile.inc

@@ -11,7 +11,6 @@ subdirs-y += ../../../cpu/x86/smm
 subdirs-y += ../../../cpu/x86/tsc
 
 bootblock-y += bootblock/bootblock.c
-bootblock-y += bootblock/cpu.c
 bootblock-y += i2c.c
 bootblock-y += bootblock/pch.c
 bootblock-y += bootblock/report_platform.c

src/soc/intel/skylake/bootblock/bootblock.c

@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <bootblock_common.h>
+#include <intelblocks/fast_spi.h>
 #include <intelblocks/gspi.h>
 #include <intelblocks/systemagent.h>
 #include <intelblocks/tco.h>
@@ -17,7 +18,7 @@ void bootblock_soc_early_init(void)
 {
 	bootblock_systemagent_early_init();
 	bootblock_pch_early_init();
-	bootblock_cpu_init();
+	fast_spi_cache_bios_region();
 	pch_early_iorange_init();
 
 	if (CONFIG(INTEL_LPSS_UART_FOR_CONSOLE))

src/soc/intel/skylake/bootblock/cpu.c

@@ -1,9 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <intelblocks/fast_spi.h>
-#include <soc/bootblock.h>
-
-void bootblock_cpu_init(void)
-{
-	fast_spi_cache_bios_region();
-}

src/soc/intel/skylake/include/soc/bootblock.h

@@ -4,7 +4,6 @@
 #define _SOC_SKYLAKE_BOOTBLOCK_H_
 
 /* Bootblock pre console init programming */
-void bootblock_cpu_init(void);
 void bootblock_pch_early_init(void);
 
 /* Bootblock post console init programming */

src/soc/intel/tigerlake/Makefile.inc

@@ -16,7 +16,6 @@ all-y += spi.c
 all-y += uart.c
 
 bootblock-y += bootblock/bootblock.c
-bootblock-y += bootblock/cpu.c
 bootblock-y += bootblock/pch.c
 bootblock-y += bootblock/report_platform.c
 bootblock-y += espi.c

src/soc/intel/tigerlake/bootblock/bootblock.c

@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <bootblock_common.h>
+#include <intelblocks/fast_spi.h>
 #include <intelblocks/systemagent.h>
 #include <intelblocks/tco.h>
 #include <intelblocks/uart.h>
@@ -16,7 +17,7 @@ void bootblock_soc_early_init(void)
 {
 	bootblock_systemagent_early_init();
 	bootblock_pch_early_init();
-	bootblock_cpu_init();
+	fast_spi_cache_bios_region();
 	pch_early_iorange_init();
 	if (CONFIG(INTEL_LPSS_UART_FOR_CONSOLE))
 		uart_bootblock_init();

src/soc/intel/tigerlake/bootblock/cpu.c

@@ -1,24 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/*
- * This file is created based on Intel Tiger Lake Processor PCH Datasheet
- * Document number: 575857
- * Chapter number: 6
- */
-
-#include <intelblocks/fast_spi.h>
-#include <soc/bootblock.h>
-
-void bootblock_cpu_init(void)
-{
-	/*
-	 * Tigerlake platform doesn't support booting from any other media
-	 * (like eMMC on APL/GLK platform) than only booting from SPI device
-	 * and on IA platform SPI is memory mapped hence enabling temporarily
-	 * cacheing on memory-mapped spi boot media.
-	 *
-	 * This assumption will not hold good for APL/GLK platform where boot
-	 * from eMMC is also possible options.
-	 */
-	fast_spi_cache_bios_region();
-}

src/soc/intel/tigerlake/include/soc/bootblock.h

@@ -4,7 +4,6 @@
 #define _SOC_TIGERLAKE_BOOTBLOCK_H_
 
 /* Bootblock pre console init programming */
-void bootblock_cpu_init(void);
 void bootblock_pch_early_init(void);
 
 /* Bootblock post console init programming */