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armv7/exynos5250/snow: deprecate CONFIG_{RAMBASE,RAMTOP} 

RAMBASE and RAMTOP are leftovers from the x86 port and do not apply
the same way on ARM platforms. On x86 they refer to the low memory
region where coreboot tables reside.

However on ARM we don't have such a region which is architecturally
defined. So instead we'll use the CPU-defined DRAM base address and
the mainboard-defined DRAM size.

This also has the pleasant side-effect of fixing the coreboot tables
to not clobber ramstage code...

Change-Id: I5548ecf05e82f9d9ecec8548fabdd99cc1e39c3b
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2351
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This commit is contained in:
David Hendricks 2013-02-10 15:50:20 -08:00 committed by Ronald G. Minnich
parent a40435af84
commit 5d994634a2
3 changed files with 8 additions and 16 deletions
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7
src/arch/armv7/coreboot_ram.ld
View File

@ -26,7 +26,7 @@ ENTRY(_start)
SECTIONS SECTIONS
{ {
. = CONFIG_RAMBASE; . = CONFIG_SYS_SDRAM_BASE;
/* First we place the code and read only data (typically const declared). /* First we place the code and read only data (typically const declared).
* This could theoretically be placed in rom. * This could theoretically be placed in rom.
*/ */
@ -123,11 +123,6 @@ SECTIONS
_ram_seg = _text; _ram_seg = _text;
_eram_seg = _eheap; _eram_seg = _eheap;
/* CONFIG_RAMTOP is the upper address of cached memory (among other
* things). We must not exceed beyond that address, there be dragons.
*/
_bogus = ASSERT( ( _eram_seg < (CONFIG_RAMTOP)) , "Please increase CONFIG_RAMTOP");
/* Discard the sections we don't need/want */ /* Discard the sections we don't need/want */
/DISCARD/ : { /DISCARD/ : {

9
src/cpu/samsung/exynos5250/Kconfig
View File

@ -90,11 +90,6 @@ config SYS_TEXT_BASE
hex "Executable code section" hex "Executable code section"
default 0x43e00000 default 0x43e00000
config RAMBASE config COREBOOT_TABLES_SIZE
hex hex
default SYS_SDRAM_BASE default 0x100000
# according to stefan, this is RAMBASE + 1M.
config RAMTOP
hex
default 0x40100000

8
src/mainboard/google/snow/ramstage.c
View File

@ -30,9 +30,11 @@ void main(void)
printk(BIOS_INFO, "hello from ramstage\n"); printk(BIOS_INFO, "hello from ramstage\n");
#if CONFIG_WRITE_HIGH_TABLES #if CONFIG_WRITE_HIGH_TABLES
/* Leave some space for ACPI tables */ /* place at top of physical memory */
high_tables_base = CONFIG_RAMBASE; high_tables_size = CONFIG_COREBOOT_TABLES_SIZE;
high_tables_size = CONFIG_RAMBASE + 0x100000; high_tables_base = CONFIG_SYS_SDRAM_BASE +
((CONFIG_DRAM_SIZE_MB * 1024) * CONFIG_NR_DRAM_BANKS) -
CONFIG_COREBOOT_TABLES_SIZE;
#endif #endif
hardwaremain(0); hardwaremain(0);