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rockchip: rk3399: init the secure setting 

set sdram, sram and all device to non-secure status,
so we can free to do mmu operation in coreboot. bl31
will care about secure control.

BRANCH=none
BUG=chrome-os-partner:51537
TEST=emerge-kevin coreboot

Change-Id: I11e02246550630c6dfe4e0cbad01e8cd5b83ef1e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ae2df532856110c4d87eb162fd3687f8de27c77f
Original-Change-Id: Ia026cf685a9d7bdf7b0c7181b1b325c54bc4554f
Original-Signed-off-by: huang lin <hl@rock-chips.com>
Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/338947
Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/14715
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Shunqian Zheng 2016-04-13 22:43:35 +08:00 committed by Patrick Georgi
parent ef2eb9df6c
commit 5dae9306d9
1 changed files with 15 additions and 0 deletions
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15
src/soc/rockchip/rk3399/bootblock.c
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@ -13,7 +13,9 @@
* GNU General Public License for more details.
*/
#include <arch/io.h>
#include <bootblock_common.h>
#include <soc/grf.h>
#include <soc/mmu_operations.h>
#include <soc/clock.h>
@ -21,5 +23,18 @@ void bootblock_soc_init(void)
{
rkclk_init();
rkclk_configure_cpu(APLL_L_600_MHZ);
/* all ddr range non-secure */
write32(&rk3399_pmusgrf->ddr_rgn_con[16], 0xff << 16 | 0);
/* tzma_rosize = 0, all sram non-secure */
write32(&rk3399_pmusgrf->soc_con4, 0x3ff << 16 | 0);
/* emmc master secure */
write32(&rk3399_pmusgrf->soc_con7, 1 << 23 | 1 << 24 | 0 << 8 | 0 << 7);
/* glb_slv_secure_bypass */
write32(&rk3399_pmusgrf->pmu_slv_con0, 1 << 16 | 1);
rockchip_mmu_init();
}