apple/imac52: add mainboard
Add Imac5,2 based on macbook2,1 port. Change-Id: I34c8313c32920b02a2b964d8718e5b2b6b5a6820 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/16638 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
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@ -0,0 +1,7 @@
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if BOARD_APPLE_IMAC52
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config MAINBOARD_PART_NUMBER
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string
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default "iMac5,2"
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endif
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config BOARD_APPLE_IMAC52
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bool "iMac5,2"
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Board name: iMac5,2
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Category: desktop
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ROM package: SOIC-8
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ROM protocol: SPI
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ROM socketed: n
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Flashrom support: n
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Clone of: apple/macbook21
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Release year: 2007
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@ -1,4 +1,4 @@
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if BOARD_APPLE_MACBOOK11 || BOARD_APPLE_MACBOOK21
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if BOARD_APPLE_MACBOOK11 || BOARD_APPLE_MACBOOK21 || BOARD_APPLE_IMAC52
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config BOARD_SPECIFIC_OPTIONS # dummy
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def_bool y
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@ -19,6 +19,7 @@
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const u32 cim_verb_data[] = {
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/* coreboot specific header */
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0x83847680, /* Codec Vendor / Device ID: SigmaTel STAC9221 A1 */
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#if CONFIG_BOARD_APPLE_MACBOOK11 || CONFIG_BOARD_APPLE_MACBOOK21
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0x106b2200, /* Subsystem ID */
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0x0000000B, /* Number of 4 dword sets */
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@ -54,6 +55,43 @@ const u32 cim_verb_data[] = {
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/* NID 0x1B. */
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AZALIA_PIN_CFG(0x0, 0x1B, 0x400000FB),
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#else /* CONFIG_BOARD_APPLE_IMAC52 */
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0x106b0f00, /* Subsystem ID */
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0x0000000b, /* Number of 4 dword sets */
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/* NID 0x01: Subsystem ID. */
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AZALIA_SUBVENDOR(0x0, 0x106b0f00),
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/* NID 0x0A. */
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AZALIA_PIN_CFG(0x0, 0x0a, 0x012be032),
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/* NID 0x0B. */
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AZALIA_PIN_CFG(0x0, 0x0b, 0x90afe111),
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/* NID 0x0C. */
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AZALIA_PIN_CFG(0x0, 0x0c, 0x9017e131),
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/* NID 0x0D. */
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AZALIA_PIN_CFG(0x0, 0x0d, 0x4080e10f),
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/* NID 0x0E. */
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AZALIA_PIN_CFG(0x0, 0x0e, 0x40f0e00f),
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/* NID 0x0F */
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AZALIA_PIN_CFG(0x0, 0x0f, 0x018be021),
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/* NID 0x10 */
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AZALIA_PIN_CFG(0x0, 0x10, 0x114bf033),
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/* NID 0x11 */
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AZALIA_PIN_CFG(0x0, 0x11, 0x11cbc022),
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/* NID 0x15 */
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AZALIA_PIN_CFG(0x0, 0x15, 0x4080e10f),
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/* NID 0x1B. */
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AZALIA_PIN_CFG(0x0, 0x1b, 0x4080e10f),
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#endif
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};
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@ -62,7 +62,7 @@ void setup_ich7_gpios(void)
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* 39: PLANARID3
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* 48: FWH_TBL#
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*/
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#if (CONFIG_BOARD_APPLE_MACBOOK11 || CONFIG_BOARD_APPLE_MACBOOK21)
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outl(0x1f40f7e2, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */
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outl(0xfea8af83, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */
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outl(0xfcc06bdf, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */
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@ -73,6 +73,18 @@ void setup_ich7_gpios(void)
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outl(0x000100c0, DEFAULT_GPIOBASE + 0x30); /* GPIO_USE_SEL2 */
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outl(0x00000030, DEFAULT_GPIOBASE + 0x34); /* GP_IO_SEL2 */
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outl(0x000100c0, DEFAULT_GPIOBASE + 0x38); /* GP_LVL2 */
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#else /* CONFIG_BOARD_APPLE_IMAC52 */
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outl(0x1f40f7c2, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */
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outl(0xfea8af83, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */
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outl(0xfcc06bff, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */
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/* Output Control Registers */
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outl(0x00000000, DEFAULT_GPIOBASE + 0x18); /* GPO_BLINK */
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/* Input Control Registers */
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outl(0x00000082, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */
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outl(0x000100c8, DEFAULT_GPIOBASE + 0x30); /* GPIO_USE_SEL2 */
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outl(0x00000030, DEFAULT_GPIOBASE + 0x34); /* GP_IO_SEL2 */
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outl(0x000100c0, DEFAULT_GPIOBASE + 0x38); /* GP_LVL2 */
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#endif
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}
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static void ich7_enable_lpc(void)
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